By default the i.MX7ULP DDR frequency runs at 352 MHz, but not all i.MX7ULP based systems are able to run at such frequency, such as the i.MX7ULP Embedded Artists board.
Introduce a CONFIG_IMX7ULP_LOWER_DDR_FREQUENCY option that allows running DDR at a lower frequency of 316.8MHz.
When such option is not selected DDR will run at the default 352MHz frequency.
Suggested-by: Bogdan Petru Chircu Mare bogdan-petru.chircu-mare@nxp.com Signed-off-by: Fabio Estevam festevam@gmail.com --- arch/arm/mach-imx/Kconfig | 7 +++++++ arch/arm/mach-imx/mx7ulp/clock.c | 27 +++++++++++++++++++++++++++ 2 files changed, 34 insertions(+)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index b0b9d2c070..bb79734738 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -89,6 +89,13 @@ config CMD_NANDBCB This is similar to kobs-ng, which is used in Linux as separate rootfs package.
+config IMX7ULP_LOWER_DDR_FREQUENCY + bool "Use lower DDR Frequency for i.MX7ULP" + depends on ARCH_MX7ULP + help + Some systems can not run DDR frequency at 352MHz, so select + this option to run DDR frequency at 316.8MHz instead + config NXP_BOARD_REVISION bool "Read NXP board revision from fuses" depends on ARCH_MX6 || ARCH_MX7 diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index d3365dd411..c26dbd3781 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -274,6 +274,31 @@ static void init_clk_rgpio2p(void) writel(PCC_CGC_MASK, (PCC0_RBASE + 0x3C)); }
+/* + * Default PFD0 divide is 27, which generates: + * PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz + * + * As some systems can not run DDR at 352MHz, use a + * divider of 30, which gives: + * + * PFD0 Freq = A7 APLL(528MHz) * 18 / 30 = 316.8MHz + */ +#define SCG1_APLL_PFD0_FRAC_NUM 30 +static void scg_a7_apll_update_pfd0(void) +{ + scg_p scg1_regs = (scg_p)SCG1_RBASE; + u32 val; + + if (!IS_ENABLED(CONFIG_IMX7ULP_LOWER_DDR_FREQUENCY)) + return; + + /* Configure A7 APLL PFD0 */ + val = readl(&scg1_regs->apllpfd); + val &= ~SCG_PLL_PFD0_FRAC_MASK; + val |= SCG1_APLL_PFD0_FRAC_NUM; + writel(val, &scg1_regs->apllpfd); +} + /* Configure PLL/PFD freq */ void clock_init(void) { @@ -300,6 +325,8 @@ void clock_init(void)
scg_a7_soscdiv_init();
+ scg_a7_apll_update_pfd0(); + scg_a7_init_core_clk();
/* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */