On 3/15/24 4:06 PM, Caleb Connolly wrote:
The Qualcomm specific dwc3 wrapper isn't hugely complicated, implemented the missing initialisation for host and gadget mode.
Reviewed-by: Mattijs Korpershoek mkorpershoek@baylibre.com Signed-off-by: Caleb Connolly caleb.connolly@linaro.org
drivers/usb/dwc3/dwc3-generic.c | 81 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 80 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index a379a0002e77..5a355dd86c60 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -424,8 +424,79 @@ enum dwc3_omap_utmi_mode { struct dwc3_glue_ops ti_ops = { .glue_configure = dwc3_ti_glue_configure, };
+/* USB QSCRATCH Hardware registers */ +#define QSCRATCH_HS_PHY_CTRL 0x10 +#define UTMI_OTG_VBUS_VALID BIT(20) +#define SW_SESSVLD_SEL BIT(28)
+#define QSCRATCH_SS_PHY_CTRL 0x30 +#define LANE0_PWR_PRESENT BIT(24)
+#define QSCRATCH_GENERAL_CFG 0x08
Keep the list sorted, 0x08 goes above 0x10 ^ up there.
+#define PIPE_UTMI_CLK_SEL BIT(0) +#define PIPE3_PHYSTATUS_SW BIT(3) +#define PIPE_UTMI_CLK_DIS BIT(8)
+#define PWR_EVNT_IRQ_STAT_REG 0x58 +#define PWR_EVNT_LPM_IN_L2_MASK BIT(4) +#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
+#define SDM845_QSCRATCH_BASE_OFFSET 0xf8800 +#define SDM845_QSCRATCH_SIZE 0x400 +#define SDM845_DWC3_CORE_SIZE 0xcd00
The rest looks fine, with that fixed:
Reviewed-by: Marek Vasut marex@denx.de
Thanks !