Dear Gabriel Huau,
In message 20120521203733.GC9379@debian you wrote:
Is it ok ? Can we apply theses patches ?
What do you mean - unfixed?
On Sun, Apr 29, 2012 at 11:27:23PM +0200, Gabriel Huau wrote:
From the last time, I removed the patch about the PLL initialization because it's board specific. I added a new patch for s3c440 gpio driver. Now in the board file we have no more magic bloat.
+/*
- When booting from NAND, it is impossible to access the lowest addresses
- due to the SteppingStone being in the way. Luckily the NOR doesn't really
- care about the highest 16 bits of address, so we set the controlers
- registers to go and poke over there, instead.
- */
+#define PHYS_FLASH_1 0x0 +#define CONFIG_SYS_FLASH_BASE 0x0
Urghh... this sounds very much like a serious design issue?
About this point, I ported it from the old version uboot as well. It may need some investigation, but I remember it was a big problem with this board. In the case of a NAND boot, we don't have access to NOR because the SteppingStone (SRAM) is mapped at the same range.
The comment and/or definitions are apparently broken, so they should be fixed / removed.
Best regards,
Wolfgang Denk