Instead of using the old-style base + offset accessors, use the new at91 C struct accessors.
The removal of #ifdef CONFIG_AT91_LEGACY allows to keep the definition of register values, needed to program the SPI.
Signed-off-by: Thomas Petazzoni thomas.petazzoni@free-electrons.com --- arch/arm/include/asm/arch-at91/at91_spi.h | 4 -- drivers/spi/atmel_dataflash_spi.c | 73 +++++++++++++++-------------- 2 files changed, 38 insertions(+), 39 deletions(-)
diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h b/arch/arm/include/asm/arch-at91/at91_spi.h index c520e89..73e23cf 100644 --- a/arch/arm/include/asm/arch-at91/at91_spi.h +++ b/arch/arm/include/asm/arch-at91/at91_spi.h @@ -33,8 +33,6 @@ typedef struct at91_spi { at91_pdc_t pdc; } at91_spi_t;
-#ifdef CONFIG_AT91_LEGACY - #define AT91_SPI_CR 0x00 /* Control Register */ #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ #define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ @@ -121,6 +119,4 @@ typedef struct at91_spi {
#define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */
-#endif /* CONFIG_AT91_LEGACY */ - #endif diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c index 4a5c4aa..c6609a0 100644 --- a/drivers/spi/atmel_dataflash_spi.c +++ b/drivers/spi/atmel_dataflash_spi.c @@ -2,6 +2,9 @@ * Driver for ATMEL DataFlash support * Author : Hamid Ikdoumi (Atmel) * + * Conversion to C struct SoC accessors by Thomas Petazzoni + * thomas.petazzoni@free-electrons.com. + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -20,10 +23,6 @@ */
#include <common.h> -#ifndef CONFIG_AT91_LEGACY -#define CONFIG_AT91_LEGACY -#warning Please update to use C structur SoC access ! -#endif #include <asm/arch/hardware.h> #include <asm/arch/clk.h> #include <asm/arch/gpio.h> @@ -40,19 +39,21 @@
void AT91F_SpiInit(void) { + at91_spi_t *spi = (at91_spi_t *) AT91_SPI0_BASE; + /* Reset the SPI */ - writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR); + writel(AT91_SPI_SWRST, &spi->cr);
/* Configure SPI in Master Mode with No CS selected !!! */ writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS, - AT91_BASE_SPI + AT91_SPI_MR); + &spi->mr);
/* Configure CS0 */ writel(AT91_SPI_NCPHA | (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - AT91_BASE_SPI + AT91_SPI_CSR(0)); + &spi->csr[0]);
#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 /* Configure CS1 */ @@ -60,7 +61,7 @@ void AT91F_SpiInit(void) (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - AT91_BASE_SPI + AT91_SPI_CSR(1)); + &spi->csr[1]); #endif #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2 /* Configure CS2 */ @@ -68,7 +69,7 @@ void AT91F_SpiInit(void) (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - AT91_BASE_SPI + AT91_SPI_CSR(2)); + &spi->csr[2]); #endif #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 /* Configure CS3 */ @@ -76,95 +77,97 @@ void AT91F_SpiInit(void) (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), - AT91_BASE_SPI + AT91_SPI_CSR(3)); + &spi->csr[3]); #endif
/* SPI_Enable */ - writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR); + writel(AT91_SPI_SPIEN, &spi->cr);
- while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS)); + while (!(readl(&spi->sr) & AT91_SPI_SPIENS));
/* * Add tempo to get SPI in a safe state. * Should not be needed for new silicon (Rev B) */ udelay(500000); - readl(AT91_BASE_SPI + AT91_SPI_SR); - readl(AT91_BASE_SPI + AT91_SPI_RDR); + readl(&spi->sr); + readl(&spi->rdr);
}
void AT91F_SpiEnable(int cs) { + at91_spi_t *spi = (at91_spi_t *) AT91_SPI0_BASE; unsigned long mode;
switch (cs) { case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */ - mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode = readl(&spi->mr); mode &= 0xFFF0FFFF; writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - AT91_BASE_SPI + AT91_SPI_MR); + &spi->mr); break; case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */ - mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode = readl(&spi->mr); mode &= 0xFFF0FFFF; writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - AT91_BASE_SPI + AT91_SPI_MR); + &spi->mr); break; case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */ - mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode = readl(&spi->mr); mode &= 0xFFF0FFFF; writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - AT91_BASE_SPI + AT91_SPI_MR); + &spi->mr); break; case 3: - mode = readl(AT91_BASE_SPI + AT91_SPI_MR); + mode = readl(&spi->mr); mode &= 0xFFF0FFFF; writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS), - AT91_BASE_SPI + AT91_SPI_MR); + &spi->mr); break; }
/* SPI_Enable */ - writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR); + writel(AT91_SPI_SPIEN, &spi->cr); }
unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc) { + at91_spi_t *spi = (at91_spi_t *) AT91_SPI0_BASE; unsigned int timeout;
pDesc->state = BUSY;
- writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR); + writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, &spi->pdc.ptcr);
/* Initialize the Transmit and Receive Pointer */ - writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR); - writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR); + writel((unsigned int)pDesc->rx_cmd_pt, &spi->pdc.rpr); + writel((unsigned int)pDesc->tx_cmd_pt, &spi->pdc.tpr);
/* Intialize the Transmit and Receive Counters */ - writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR); - writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR); + writel(pDesc->rx_cmd_size, &spi->pdc.rcr); + writel(pDesc->tx_cmd_size, &spi->pdc.tcr);
if (pDesc->tx_data_size != 0) { /* Initialize the Next Transmit and Next Receive Pointer */ - writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR); - writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR); + writel((unsigned int)pDesc->rx_data_pt, &spi->pdc.pnpr); + writel((unsigned int)pDesc->tx_data_pt, &spi->pdc.tnpr);
/* Intialize the Next Transmit and Next Receive Counters */ - writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR); - writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR); + writel(pDesc->rx_data_size, &spi->pdc.pncr); + writel(pDesc->tx_data_size, &spi->pdc.tncr); }
/* arm simple, non interrupt dependent timer */ reset_timer_masked(); timeout = 0;
- writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR); - while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) && + writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, &spi->pdc.ptcr); + while (!(readl(&spi->sr) & AT91_SPI_RXBUFF) && ((timeout = get_timer_masked()) < CONFIG_SYS_SPI_WRITE_TOUT)); - writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR); + writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, &spi->pdc.ptcr); pDesc->state = IDLE;
if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {