Signed-off-by: Marcel Ziswiler marcel@ziswiler.com --- cpu/pxa/start.S | 38 +++++++++++++++++++------------------- doc/README.nand | 2 +- drivers/net/ne2000.c | 7 +++---- include/linux/mtd/nand.h | 2 +- nand_spl/nand_boot.c | 2 +- 5 files changed, 25 insertions(+), 26 deletions(-)
diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index b922485..31f408d 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -57,7 +57,7 @@ _fiq: .word fiq * Startup Code (reset vector) * * do important init only if we don't start from RAM! - * - relocate armboot to ram + * - relocate armboot to RAM * - setup stack * - jump to second stage */ @@ -90,7 +90,7 @@ IRQ_STACK_START: .globl FIQ_STACK_START FIQ_STACK_START: .word 0x0badc0de -#endif +#endif /* CONFIG_USE_IRQ */
/****************************************************************************/ @@ -100,18 +100,18 @@ FIQ_STACK_START: /****************************************************************************/
reset: - mrs r0,cpsr /* set the cpu to SVC32 mode */ + mrs r0,cpsr /* set the CPU to SVC32 mode */ bic r0,r0,#0x1f /* (superviser mode, M=10011) */ orr r0,r0,#0x13 msr cpsr,r0
/* * we do sys-critical inits only at reboot, - * not when booting from ram! + * not when booting from RAM! */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit /* we do sys-critical inits */ -#endif +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ @@ -130,7 +130,7 @@ copy_loop: stmia r1!, {r3-r10} /* copy to target address [r1] */ cmp r0, r2 /* until source end addreee [r2] */ ble copy_loop -#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ +#endif /* !CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */ stack_setup: @@ -139,7 +139,7 @@ stack_setup: sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) -#endif +#endif /* CONFIG_USE_IRQ */ sub sp, r0, #12 /* leave 3 words for abort-stack */
clear_bss: @@ -172,11 +172,11 @@ _start_armboot: .word start_armboot #undef OSCR #undef OWER #undef OIER -#endif +#endif /* CONFIG_PXA250 || CONFIG_CPU_MONAHANS */ #ifdef CONFIG_PXA250 #undef RCSR #undef CCCR -#endif +#endif /* CONFIG_PXA250 */
/* Interrupt-Controller base address */ IC_BASE: .word 0x40d00000 @@ -197,18 +197,18 @@ OSTIMER_BASE: .word 0x40a00000 #ifdef CONFIG_CPU_MONAHANS # ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO # error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!" -# endif +# endif /* !CFG_MONAHANS_RUN_MODE_OSC_RATIO */ # ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO # define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1 -# endif -#else /* ! CONFIG_CPU_MONAHANS */ +# endif /* !CFG_MONAHANS_TURBO_RUN_MODE_RATIO */ +#else /* !CONFIG_CPU_MONAHANS */ #ifdef CFG_CPUSPEED CC_BASE: .word 0x41300000 #define CCCR 0x00 cpuspeed: .word CFG_CPUSPEED -#else +#else /* !CFG_CPUSPEED */ #error "You have to define CFG_CPUSPEED!!" -#endif +#endif /* CFG_CPUSPEED */ #endif /* CONFIG_CPU_MONAHANS */
/* takes care the CP15 update has taken place */ @@ -225,7 +225,7 @@ cpu_init_crit: ldr r0, IC_BASE mov r1, #0x00 str r1, [r0, #ICMR] -#else +#else /* CONFIG_CPU_MONAHANS */ /* Step 1 - Enable CP6 permission */ mrc p15, 0, r1, c15, c1, 0 @ read CPAR orr r1, r1, #0x40 @@ -244,14 +244,14 @@ cpu_init_crit: ldr r1, =CKENB ldr r2, =(CKENB_6_IRQ) str r2, [r1] -#endif +#endif /* !CONFIG_CPU_MONAHANS */
/* set clock speed */ #ifdef CONFIG_CPU_MONAHANS ldr r0, =ACCR ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK)) str r1, [r0] -#else /* ! CONFIG_CPU_MONAHANS */ +#else /* !CONFIG_CPU_MONAHANS */ #ifdef CFG_CPUSPEED ldr r0, CC_BASE ldr r1, cpuspeed @@ -451,7 +451,7 @@ fiq: bl do_fiq /* effiction fiq_save_user_regs */ irq_restore_user_regs
-#else +#else /* !CONFIG_USE_IRQ */
.align 5 irq: @@ -465,7 +465,7 @@ fiq: bad_save_user_regs bl do_fiq
-#endif +#endif /* CONFIG_USE_IRQ */
/****************************************************************************/ /* */ diff --git a/doc/README.nand b/doc/README.nand index c5c5ef2..647a6b8 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -79,7 +79,7 @@ Commands:
nand write.jffs2 addr ofs|partition size Like `write', but blocks that are marked bad are skipped and the - is written to the next block instead. This allows writing writing + data is written to the next block instead. This allows writing a JFFS2 image, as long as the image is short enough to fit even after skipping the bad blocks. Compact images, such as those produced by mkfs.jffs2 should work well, but loading an image copied diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c index c978d62..b100657 100644 --- a/drivers/net/ne2000.c +++ b/drivers/net/ne2000.c @@ -839,7 +839,7 @@ void uboot_push_packet_len(int len) { } dp83902a_recv(&pbuf[0], len);
- /*Just pass it to the upper layer*/ + /* Just pass it to the upper layer */ NetReceive(&pbuf[0], len); }
@@ -902,7 +902,6 @@ int eth_init(bd_t *bd) { }
void eth_halt() { - PRINTK("### eth_halt\n"); if(initialized) dp83902a_stop(); @@ -910,8 +909,8 @@ void eth_halt() { }
int eth_rx() { -dp83902a_poll(); -return 1; + dp83902a_poll(); + return 1; }
int eth_send(volatile void *packet, int length) { diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 49ff80f..4cc4a7d 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -129,7 +129,7 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_ #define NAND_ECC_HW3_256 2 /* Hardware ECC 3 byte ECC per 512 Byte data */ #define NAND_ECC_HW3_512 3 -/* Hardware ECC 3 byte ECC per 512 Byte data */ +/* Hardware ECC 6 byte ECC per 512 Byte data */ #define NAND_ECC_HW6_512 4 /* Hardware ECC 8 byte ECC per 512 Byte data */ #define NAND_ECC_HW8_512 6 diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c index 840a596..e2147cb 100644 --- a/nand_spl/nand_boot.c +++ b/nand_spl/nand_boot.c @@ -73,7 +73,7 @@ static int nand_is_bad_block(struct mtd_info *mtd, int block) nand_command(mtd, block, 0, CFG_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
/* - * Read on byte + * Read one byte */ if (this->read_byte(mtd) != 0xff) return 1;