From: Ang, Chee Hong chee.hong.ang@intel.com Sent: Friday, July 10, 2020 8:55 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; See, Chin Liang chin.liang.see@intel.com; Tan, Ley Foon ley.foon.tan@intel.com; Ang, Chee Hong chee.hong.ang@intel.com Subject: [PATCH v1 3/4] clk: agilex: Handle clock configuration differently in SPL and U-Boot proper
Since warm reset may optionally set the CLock Manager to'boot mode', the clock driver should always force the Agilex's Clock Manager to 'boot
mode'
before the clock driver start configuring the Clock Manager in SPL. In SSBL, clock driver will skip the Clock Manager configuration if it's already being setup by SPL (Clock Manager NOT in 'boot mode') to prevent any inaccurate clocking issues happened on HPS peripherals such as UART, MAC and etc.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com
drivers/clk/altera/clk-agilex.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index b5cf187364..c83eb2efb9 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -171,6 +171,16 @@ static void clk_basic_init(struct udevice *dev, if (!cfg) return;
+#ifdef CONFIG_SPL_BUILD
- /* Always force clock manager into boot mode before any
configuration */
- clk_write_ctrl(plat,
CM_REG_READL(plat, CLKMGR_CTRL) |CLKMGR_CTRL_BOOTMODE); #else
"#else" is at the end of line, is this patch display issue or coding issue?
Only happen in display. Code is fine.
Regards Ley Foon