Dear York Sun,
In message 1363973052-25918-19-git-send-email-yorksun@freescale.com you wrote:
From: Liu Gang Gang.Liu@freescale.com
When boot from PCIE or SRIO, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE or SRIO interface.
Slave's ucode and ENV can be stored in master's memory space, then slave can fetch them through PCIE or SRIO interface.
...
CHECK: Alignment should match open parenthesis #180: FILE: board/freescale/b4860qds/tlb.c:61: + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
CHECK: Alignment should match open parenthesis #196: FILE: board/freescale/b4860qds/tlb.c:155: + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
Best regards,
Wolfgang Denk