This patch adds U-Boot support for the Reachtech G2C1 board. G2C1 U-Boot images created with this patch will perform the following: - Initialise the MX28 for 'No Battery' mode - Configure all IOMUXs - Configure GPIO directions for all IOMUXs designed for GPIO use - Inilialise the MMC sub-system - Initialise the Ethernet sub-system
NOTE: The 'arm: mxs: Enable booting of mx28 without battery' patch MUST be applied prior to building G2C1 images using this patch
Refer to the README file for detailed documentation
Signed-off-by: Graeme Russ gruss@tss-engineering.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Stefano Babic sbabic@denx.de Cc: Marek Vasut marex@denx.de Cc: u-boot@lists.denx.de Cc: Brent Larson blarson@reachtech.com Cc: Jonathan More jmore@reachtech.com Cc: Jeff Horn jhorn@reachtech.com Cc: Wolfgang Denk wd@denx.de
--- Changes in v2 - Moved IOMUX documenations into README file - Expanded README file to cover considerably more information - Setup all GPIO pins in g2c1.c - Created two configurations - g2c1_mmc_defconfig for building for MMC image and g2c1_nand_defconfig for building NAND image - Fixed up Ethernet initialisation
arch/arm/Kconfig | 13 ++ board/reachtech/g2c1/Kconfig | 15 ++ board/reachtech/g2c1/MAINTAINERS | 7 + board/reachtech/g2c1/Makefile | 12 ++ board/reachtech/g2c1/README | 438 +++++++++++++++++++++++++++++++++++++++ board/reachtech/g2c1/g2c1.c | 142 +++++++++++++ board/reachtech/g2c1/spl_boot.c | 236 +++++++++++++++++++++ configs/g2c1_mmc_defconfig | 4 + configs/g2c1_nand_defconfig | 4 + include/configs/g2c1.h | 307 +++++++++++++++++++++++++++ 10 files changed, 1178 insertions(+) create mode 100644 board/reachtech/g2c1/Kconfig create mode 100644 board/reachtech/g2c1/MAINTAINERS create mode 100644 board/reachtech/g2c1/Makefile create mode 100644 board/reachtech/g2c1/README create mode 100644 board/reachtech/g2c1/g2c1.c create mode 100644 board/reachtech/g2c1/spl_boot.c create mode 100644 configs/g2c1_mmc_defconfig create mode 100644 configs/g2c1_nand_defconfig create mode 100644 include/configs/g2c1.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5eb1d03..320041e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -278,6 +278,18 @@ config TARGET_XFI3 select CPU_ARM926EJS select SUPPORT_SPL
+config TARGET_G2C1 + bool "Support ReachTech G2C1" + select CPU_ARM926EJS + select SUPPORT_SPL + help + This is the Reachtech G2C1 development board. It contains a + Freescale MX28 SoC, 128MB DDR2 SDRAM, 128MB SLC NAND, 1x Ethernet + port, 2x USB Host ports, 1x USB OTG port, 1x RS-232 Debug port, + 1x RS-232 User port, 2x RS485 ports, Onboard audio, LCD Touch + screen interface, SD Card slot, I2C and SPI (with 2x slave select + lines) interfaces, CAN interface, and 8 GPIO (I2C slave interface) + config TARGET_M28EVK bool "Support m28evk" select CPU_ARM926EJS @@ -940,6 +952,7 @@ source "board/phytec/pcm051/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/pxa255_idp/Kconfig" source "board/raspberrypi/rpi/Kconfig" +source "board/reachtech/g2c1/Kconfig" source "board/ronetix/pm9261/Kconfig" source "board/ronetix/pm9263/Kconfig" source "board/ronetix/pm9g45/Kconfig" diff --git a/board/reachtech/g2c1/Kconfig b/board/reachtech/g2c1/Kconfig new file mode 100644 index 0000000..5ef821f --- /dev/null +++ b/board/reachtech/g2c1/Kconfig @@ -0,0 +1,15 @@ +if TARGET_G2C1 + +config SYS_BOARD + default "g2c1" + +config SYS_VENDOR + default "reachtech" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "g2c1" + +endif diff --git a/board/reachtech/g2c1/MAINTAINERS b/board/reachtech/g2c1/MAINTAINERS new file mode 100644 index 0000000..257888b --- /dev/null +++ b/board/reachtech/g2c1/MAINTAINERS @@ -0,0 +1,7 @@ +G2C1 BOARD +M: Graeme Russ gruss@tss-engineering.com +S: Maintained +F: board/reachtech/g2c1/ +F: include/configs/mx28evk.h +F: configs/g2c1_mmcconfig +F: configs/g2c1_nandconfig diff --git a/board/reachtech/g2c1/Makefile b/board/reachtech/g2c1/Makefile new file mode 100644 index 0000000..9bb55e8 --- /dev/null +++ b/board/reachtech/g2c1/Makefile @@ -0,0 +1,12 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_SPL_BUILD +obj-y := g2c1.o +else +obj-y := spl_boot.o +endif diff --git a/board/reachtech/g2c1/README b/board/reachtech/g2c1/README new file mode 100644 index 0000000..745bcdc --- /dev/null +++ b/board/reachtech/g2c1/README @@ -0,0 +1,438 @@ +ReachTech G2C1 +================== + +Supported hardware: ReachTech G2C1 + +Reference Documentation +----------------------- +doc/README.mxs + +Files of the G2C1 port +-------------------------- +arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28 +arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28 +board/reachtech/g2c1/ - G2C1 board specific files +include/configs/g2c1.h - G2C1 configuration file +configs/g2c1_mmc_config - G2C1 MMC Target configuration file +configs/g2c1_nand_config - G2C1 NAND Target configuration file + +2) Compiling U-Boot for a MXS based board +------------------------------------------- +doc/README.mxs contains detailed information for compiling U-Boot for mx28 +based boards. The following instructions are a minimal set of instructions +required to build a U-Boot image for the G2C1 board. + +Step 0) - Ensure the 'MXS No Battery' Patch is applied +Refer below to 'No LiIon Battery' in the 'G2C1 Features' of this README + +Step 1) - Clean +Clean the U-Boot build tree of all stale output files by running the following +command: + + $ make mrproper + +Step 2) - Configure +Configure the U-Boot build system to build either an MMC or NAND image by +running one of the following commands: + + $ make g2c1_mmc_config + +or; + + $ make g2c1_nand_config + +NOTE: The environment variables will be stored on the same target as the U-Boot +image. i.e. running 'make g2c1_mmc_config' will generate a U-Boot image with +the environment stored on the MMC card. + +Step 3) - Build U-Boot +Compile U-Boot and prepare an MXS "BootStream" by running the following +command: + + $ make u-boot.sb + +Step 4) - Prepare Image +Prepare the "BootStream" for writing to the SD card or NAND flash + + - If preparing an SD card image, run the following command: + + $ ./tools/mxsboot sd u-boot.sb u-boot.sd + + - If preparing a NAND flash image, run the following command: + + $ ./tools/mxsboot nand u-boot.sb u-boot.nand + +Step 5) - Install Image +Write the processed "BootStream" to the SD card or NAND flash (Refer to +doc/README.mxs for instructions) + +U-Boot Environment Storage +-------------------------- +The U-Boot environment variable will be stored either on the SD/MMC card or in +NAND flash depending on the configuration selected in step 2 of the build +process. The U-Boot environment size is configured to 16Kib. + +SD/MMC: +If the environment is stored on the SD/MMC card, the environment will be stored +at the end of the partition reserved for U-Boot (see doc/README.mxs) + +NAND: +If the environment is stored in NAND flash, the environment will be stored at +an offset of 3MiB from the beginning of the NAND flash. 4 NAND Pages (512KiB) +are reserved for each of the primary and redundant environment stores (the +additional space allows for bad NAND blocks) + +Jumper configuration +--------------------- +Pins 3 & 4 of JP2 determine if the board boots from an SD Card or the +onboard NAND Flash: + - Jumper in - Boot from NAND Flash + - Jumper out - Boot from SD Card + +G2C1 Features +------------- + - No LiIon Battery + The G2C1 board does not contain a 4.2v lithium ion battery (refer to + Freescale Application Note AN4199). The U-Boot patch 'arm: mxs: Enable + booting of mx28 without battery' MUST be applied in order for the G2C1 + board to boot. + + - Run Led + GPIO Bank 3, Pin 27 controls the board's Run LED. This output is Active Low + U-Boot turns on the Run LED after SPL has completed and U-Boot has been + loaded into memory + + - NAND Write Protect + NAND can be write protected via hardware (by inserting a jumper across pins + 1 and 2 of J2) or software (by setting GPIO Bank 0, Pin 28 to logic 0). NAND + write protected if EITHER of the two mechanisms are active. + + WARNING: U-Boot disabled the software NAND write protect (in order to allow + U-Boot to write updated U-Boot images to the NAND) + + - 8-bit GPIO with Interrupt + The G2C1 includes a PCA9534 '8-bit I 2 C-bus and SMBus low power I/O port + with interrupt' to provide 8 configurable digital GPIO pins. The interrupt + output of the PCA9534 is connected to GPIO Bank 0, Pin 18 + + - RTC + The G2C1 includes a PCF8523 'Real-Time Clock (RTC) and calendar' connected + to the I2C bus (slave address 0b1101000). The interrupt output of the + PCF8523 is NOT connected to any MX28 input. + + NOTE: The G2C1 schematics document the I2C slave address of this device + being 0b0111110. However, the PCA9534 data sheet states that the slave + address is 0b0100xxx, with the 3 LSBs set via hardware (in the case of the + G2C1, the LSBs are set to 110). Therefore, the slave address might actually + be 0b0100110, not 0b0111110. + + - LCD Panel + Power to the LCD panel can be turned off by setting GPIO Bank 3, Pin 30 to + logic 0. + + The LCD backlight is enabled by setting GPIO Bank 3, Pin 2 to logic 1 + Backlight brightness is controlled by PWM3 + + The LCD display is enabled by setting GPIO Bank 0, Pin 19 to logic 1 + + - Debug Port CTS + The CTS line of the RS-232 Debug port is controlled by GPIO Bank 2, Pin 5. + U-Boot sets the Debug Port CTS to logic 1 (enabled) + + - Ethernet + The G2C1 board utilises a LAN8720A 'Small Footprint RMII 10/100 Ethernet + Transceiver with HP Auto-MDIX Support' PHY. The PHY can be reset by holding + GPIO Bank 3, Pin 20 at logic 0 for a minimum of 100us + + The Interrupt output of the PHY is connected to GPIO Bank 2, Pin 6. This + input is active low + + - USB (General) + The G2C1 utilises a USB2512B 'USB 2.0 Hi-Speed Hub Controller' to provide + two USB host ports. The USB2512B is connect to USB1 of the MX28, while USB0 + is connected to the USB OTG port. + + - USB OTG Power Enable + Power to the USB OTG connector is enabled by setting GPIO Bank 2, Pin 4 to + logic level 1. U-Boot disables power to the USB OTG connector + + - USB Overcurrent (USB OTG Only) + Only the USB OTG port is monitored for overcurrent condition. In the event + of an overcurrent detected on the USB OTG port, the USB0_OVRCURRENT input of + the MX28 will be asserted (active low input) + + - USB Reset (USB1 Only) + The USB2512B Hub Controller can be reset by by holding GPIO Bank 2, Pin 7 at + logic 0 for a minimum of 1us + + - Onboard Audio + The G2C1 board includes an onboard speaker. Pitch and volume of the audio + output is controlled via PWM4 and PWM7 + + NOTE: Consult Rechtech regarding generating audio using PWM4 and PWM7 + +What Isn't Implemented +---------------------- + - Control of 8-bit GPIO (No U-Boot driver for the PCA9534) + - External RTC (No U-Boot driver for the PCF8523) + - LCD Backlight control (see Note) + - Onboard Audio control (see Note) + - Change state of Software Write Protect of NAND (can probably be done via + the gpio command) + +NOTE: LCD Backlight and Onboard Audio control control require configuration of +the MXS PWMs + +IOMUX Configuration +------------------- +Bank. SoC +Pin Pin Function Comments +-------------------------------------------------------------------------- +0.0 U8 GPMI_D0 +0.1 T8 GPMI_D1 +0.2 R8 GPMI_D2 +0.3 U7 GPMI_D3 +0.4 T7 GPMI_D4 +0.5 R7 GPMI_D5 +0.6 U6 GPMI_D6 +0.7 T6 GPMI_D7 +0.8 - - Reserved +0.9 - - Reserved +0.10 - - Reserved +0.11 - - Reserved +0.12 - - Reserved +0.13 - - Reserved +0.14 - - Reserved +0.15 - - Reserved +0.16 N7 GPMI_CE0N +0.17 N9 GPMI_CE1N +0.18 M7 GPIO_INTERUPT GPIO, Input, 3V3, 4mA, External Pullup +0.19 M9 DISP_ON GPIO, Output, 3V3, 4mA, No Pollup +0.20 N6 GPMI_READY0 +0.21 N8 GPMI_READY1 +0.22 M8 CAN0_TX +0.23 L8 CAN0_RX +0.24 R6 GPMI_RDN +0.25 P8 GPMI_WRN +0.26 P6 GPMI_ALE +0.27 P7 GPMI_CLE +0.28 L9 NAND_WP GPIO, 3V3, 4mA, External Pullup, Active Low +0.29 - - Reserved +0.30 - - Reserved +0.31 - - Reserved + +Bank. SoC +Pin Pin Function Comments +-------------------------------------------------------------------------- +1.0 K2 LCD_D0 +1.1 K3 LCD_D1 +1.2 L2 LCD_D2 +1.3 L3 LCD_D3 +1.4 M2 LCD_D4 +1.5 M3 LCD_D5 +1.6 N2 LCD_D6 +1.7 P1 LCD_D7 +1.8 P2 LCD_D8 +1.9 P3 LCD_D9 +1.10 R1 LCD_D10 +1.11 R2 LCD_D11 +1.12 T1 LCD_D12 +1.13 T2 LCD_D13 +1.14 U2 LCD_D14 +1.15 U3 LCD_D15 +1.16 T3 LCD_D16 +1.17 R3 LCD_D17 +1.18 U4 LCD_D18 +1.19 T4 LCD_D19 +1.20 R4 LCD_D20 +1.21 U5 LCD_D21 +1.22 T5 LCD_D22 +1.23 R5 LCD_D23 +1.24 P4 LCD_VSYNC +1.25 K1 LCD_HSYNC +1.26 M4 LCD_DOTCLK +1.27 P5 LCD_ENABLE +1.28 L1 LCD_VSYNC Not Connected +1.29 M1 LCD_HSYNC Not Connected +1.30 N1 LCD_DOTCLK Not Connected +1.31 N5 LCD_ENABLE Not Connected + * +Bank. SoC +Pin Pin Function Comments +-------------------------------------------------------------------------- +2.0 B6 SSP0_D0 +2.1 C6 SSP0_D1 +2.2 D6 SSP0_D2 +2.3 A5 SSP0_D3 +2.4 B5 USB_0_PWR_EN GPIO, Output, 3V3, 4mA, External Pulldown +2.5 C5 DUART_CTS GPIO, Output, 3V3, 4mA, External Pullup +2.6 D5 ENET_INT GPIO, Input, 3V3, 4mA, External Pullup +2.7 B4 USB_RESET_B GPIO, Output, 3V3, 4mA, External Pullup +2.8 A4 SSP0_CMD +2.9 D10 SSP0_CARD_DTCT +2.10 A6 SSP0_SCK +2.11 - - Reserved +2.12 B1 SSP1_SCK Not Connected +2.13 C1 SSP1_CMD Not Connected +2.14 D1 SSP1_DATA0 Not Connected +2.15 E1 SSP1_DATA3 Not Connected +2.16 A3 SSP2_SCK SPI Clock - 3V3, 4mA, No Pullup +2.17 C3 SSP2_MOSI SPI MOSI - 3V3, 4mA, No Pullup +2.18 B3 SSP2_MISO SPI MISO - 3V3, 4mA, No Pullup +2.19 C4 SSP2_SS0 SPI Slave Select 0 - 3V3, 4mA, No Pullup +2.20 D3 SSP2_SS1 SPI Slave Select 1 - 3V3, 4mA, No Pullup +2.21 D4 USB0_OVRCURRENT USB Overcurrent +2.22 - - Reserved +2.23 - - Reserved +2.24 A2 SSP3_SCK Not Connected +2.25 C2 SSP3_MOSI Not Connected +2.26 B2 SSP3_MISO Not Connected +2.27 D2 SSP3_SS0 Not Connected +2.28 - - Reserved +2.29 - - Reserved +2.30 - - Reserved +2.31 - - Reserved + +Bank. SoC +Pin Pin Function Comments +-------------------------------------------------------------------------- +3.0 G5 AUART0_RX RS485 +3.1 H5 AUART0_TX RS485 +3.2 J6 BACKLIGHT_EN GPIO, Output, 3V3, 4mA, External Pulldown +3.3 J7 AUART0_RTS RS485 +3.4 L4 AUART1_RX +3.5 K4 AUART1_TX +3.6 K5 AUART1_CTS Not Connected +3.7 J5 AUART1_RTS Not Connected +3.8 F6 AUART2_RX Not Connected +3.9 F5 AUART2_TX Not Connected +3.10 H6 AUART2_CTS Not Connected +3.11 H7 AUART2_RTS Not Connected +3.12 M5 AUART3_RX Not Connected +3.13 L5 AUART3_TX Not Connected +3.14 L6 AUART3_CTS Not Connected +3.15 K6 AUART3_RTS Not Connected +3.16 K7 I2C1_SCL +3.17 L7 I2C1_SDA +3.18 K8 USB0_ID USB OTG ID +3.19 - - Reserved +3.20 G7 ENET_FEC_RESET GPIO, Output, 3V3, 4mA, External Pullup, Active Low +3.21 G6 AUART4_RTS RS485 hardware issue +3.22 F7 AUART4_RX RS485 hardware issue +3.23 E7 AUART4_TX RS485 hardware issue +3.24 C7 DUART_RX +3.25 D8 DUART_TX +3.26 E8 PWM7 Onboard Audio (Frequency or Volume?) +3.27 D7 RUN_LED GPIO, Output, 3V3, Active Low +3.28 E9 PWM_3 LCD Backlight Brightness +3.29 E10 PWM_4 Onboard Audio (Frequency or Volume?) +3.30 M6 LCD_PWR_EN GPIO, Output, 3V3, 4mA, External Pullup +3.31 - - Reserved + +Bank. SoC +Pin Pin Function Comments +-------------------------------------------------------------------------- +4.0 G4 ENET0_MDC 3V3, 4mA, Internal Pullup +4.1 H4 ENET0_MDIO 3V3, 4mA, Internal Pullup +4.2 E4 ENET0_RX_EN 3V3, 4mA, Internal Pullup +4.3 H1 ENET0_RXD0 3V3, 4mA, Internal Pullup +4.4 H2 ENET0_RXD1 3V3, 4mA, Internal Pullup +4.5 E3 ENET0_TX_CLK Not Connected +4.6 F4 ENET0_TX_EN +4.7 F1 ENET0_TXD0 +4.8 F2 ENET0_TXD1 +4.9 J1 ENET0_RX_D2 Not Connected +4.10 J2 ENET0_RX_D3 Not Connected +4.11 G1 ENET0_TX_D2 Not Connected +4.12 G2 ENET0_TX_D2 Not Connected +4.13 F3 ENET0_RX_CLK Not Connected +4.14 J4 ENET0_COL Not Connected +4.15 J3 ENET0_CRS Not Connected +4.16 E2 CLKCTRL_ENET +4.17 - - Reserved +4.18 - - Reserved +4.19 - - Reserved +4.20 E14 JTAG_RTCK 3V3, 4mA, External Pullup +4.21 - - Reserved +4.22 - - Reserved +4.23 - - Reserved +4.24 - - Reserved +4.25 - - Reserved +4.26 - - Reserved +4.27 - - Reserved +4.28 - - Reserved +4.29 - - Reserved +4.30 - - Reserved +4.31 - - Reserved + +Bank. SoC +Pin Pin Function Comments +-------------------------------------------------------------------------- +5.0 N16 EMI_DATA0 +5.1 M13 EMI_DATA1 +5.2 P15 EMI_DATA2 +5.3 N14 EMI_DATA3 +5.4 P13 EMI_DATA4 +5.5 P17 EMI_DATA5 +5.6 L14 EMI_DATA6 +5.7 M17 EMI_DATA7 +5.8 G16 EMI_DATA8 +5.9 H15 EMI_DATA9 +5.10 G14 EMI_DATA10 +5.11 J14 EMI_DATA11 +5.12 H13 EMI_DATA12 +5.13 H17 EMI_DATA13 +5.14 F13 EMI_DATA14 +5.15 F17 EMI_DATA15 +5.16 R17 EMI_ODT0 +5.17 M15 EMI_DQM0 +5.18 T17 EMI_ODT1 Not Connected +5.19 F15 EMI_DQM1 +5.20 L15 EMI_DDR_OPEN_FB +5.21 L16/L17 EMI_CLK +5.22 K16/K17 EMI_DQS0 +5.23 J16/J17 EMI_DQS1 +5.24 - - Reserved +5.25 - - Reserved +5.26 K14 EMI_DDR_OPEN +5.27 - - Reserved +5.28 - - Reserved +5.29 - - Reserved +5.30 - - Reserved +5.31 - - Reserved + +Bank. SoC +Pin Pin Function Comments +-------------------------------------------------------------------------- +6.0 U15 EMI_ADDR0 +6.1 U12 EMI_ADDR1 +6.2 U14 EMI_ADDR2 +6.3 T11 EMI_ADDR3 +6.4 U10 EMI_ADDR4 +6.5 R11 EMI_ADDR5 +6.6 R9 EMI_ADDR6 +6.7 N11 EMI_ADDR7 +6.8 U9 EMI_ADDR8 +6.9 P10 EMI_ADDR9 +6.10 U13 EMI_ADDR10 +6.11 T10 EMI_ADDR11 +6.12 U11 EMI_ADDR12 +6.13 T9 EMI_ADDR13 +6.14 N10 EMI_ADDR14 +6.15 - - Reserved +6.16 T16 EMI_BA0 +6.17 T12 EMI_BA1 +6.18 N12 EMI_BA2 +6.19 U16 EMI_CASN +6.20 R16 EMI_RASN +6.21 T15 EMI_WEN +6.22 P12 EMI_CE0N +6.23 P9 EMI_CE1N Not Connected +6.24 T13 EMI_CKE +6.25 - - Reserved +6.26 - - Reserved +6.27 - - Reserved +6.28 - - Reserved +6.29 - - Reserved +6.30 - - Reserved +6.31 - - Reserved diff --git a/board/reachtech/g2c1/g2c1.c b/board/reachtech/g2c1/g2c1.c new file mode 100644 index 0000000..b54dbc6 --- /dev/null +++ b/board/reachtech/g2c1/g2c1.c @@ -0,0 +1,142 @@ +/* + * Reachtech G2C1 board + * + * Copyright (C) 2015 Graeme Russ gruss@tss-engineering.com + * on behalf of DENX Software Engineering GmbH + * + * Author: Graeme Russ gruss@tss-engineering.com + * + * Based on m28evk.c: + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <linux/mii.h> +#include <miiphy.h> +#include <netdev.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + /* SSP2 clock at 160MHz */ + mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); + + /* Turn the Run LED On */ + gpio_direction_output(MX28_PAD_SPDIF__GPIO_3_27, 0); + + /* Turn off software write protect of NAND */ + gpio_direction_output(MX28_PAD_GPMI_RESETN__GPIO_0_28, 1); + + /* Power on LCD */ + gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 1); + + /* Enable the LCD display */ + gpio_direction_output(MX28_PAD_GPMI_CE3N__GPIO_0_19, 1); + + /* Turn on the LCD backlight */ + gpio_direction_output(MX28_PAD_AUART0_CTS__GPIO_3_2, 1); + + /* TODO: Set the LCD backlight to maximum brightness */ + + /* Disbale power to the USB OTG Port */ + gpio_direction_output(MX28_PAD_SSP0_DATA4__GPIO_2_4, 0); + + /* Turn on DEBUG port CTS */ + gpio_direction_output(MX28_PAD_SSP0_DATA5__GPIO_2_5, 1); + + /* Configure the Ethernet Interrupt Input */ + gpio_direction_input(MX28_PAD_SSP0_DATA6__GPIO_2_6); + + /* Configure the 8-bit GPIO Interrupt Input */ + gpio_direction_input(MX28_PAD_GPMI_CE2N__GPIO_0_18); + + + return 0; +} + +int dram_init(void) +{ + return mxs_dram_init(); +} + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_CMD_MMC + +int board_mmc_init(bd_t *bis) +{ + return mxsmmc_initialize(bis, 0, NULL, NULL); +} +#endif + +#ifdef CONFIG_CMD_NET + +#define MII_OPMODE_STRAP_OVERRIDE 0x16 +#define MII_PHY_CTRL1 0x1e +#define MII_PHY_CTRL2 0x1f + +int board_eth_init(bd_t *bis) +{ + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct eth_device *dev; + int ret; + + ret = cpu_eth_init(bis); + if (ret) + return ret; + + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet, + CLKCTRL_ENET_TIME_SEL_MASK, + CLKCTRL_ENET_TIME_SEL_RMII_CLK | + CLKCTRL_ENET_CLK_OUT_EN); + + /* Reset the PHY */ + gpio_direction_output(MX28_PAD_SAIF0_MCLK__GPIO_3_20, 0); + mdelay(10); + gpio_set_value(MX28_PAD_SAIF0_MCLK__GPIO_3_20, 1); + mdelay(10); + + ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); + if (ret) { + printf("FEC MXS: Unable to init FEC0\n"); + return ret; + } + + dev = eth_get_dev_by_name("FEC0"); + if (!dev) { + printf("FEC MXS: Unable to get FEC0 device entry\n"); + return -EINVAL; + } + + return ret; +} + +#endif diff --git a/board/reachtech/g2c1/spl_boot.c b/board/reachtech/g2c1/spl_boot.c new file mode 100644 index 0000000..bca9dad --- /dev/null +++ b/board/reachtech/g2c1/spl_boot.c @@ -0,0 +1,236 @@ +/* + * DENX M28 Boot setup + * + * Copyright (C) 2011 Marek Vasut marek.vasut@gmail.com + * on behalf of DENX Software Engineering GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +#define MUX_CONFIG_I2C (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_SPI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_CAN (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_JTAG (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_UART (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_GPIO (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_PWM (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) + +const iomux_cfg_t iomux_setup[] = { + /* Run LED */ + MX28_PAD_SPDIF__GPIO_3_27 | MUX_CONFIG_LED, + + /* JTAG */ + MX28_PAD_JTAG_RTCK__JTAG_RTCK | MUX_CONFIG_JTAG, + + /* LCD Framebuffer */ + MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, + MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_CS__LCD_ENABLE | MUX_CONFIG_LCD, + + /* LCD Panel Power Enable */ + MX28_PAD_LCD_RESET__GPIO_3_30 | (MXS_PAD_3V3 | MXS_PAD_4MA), + + /* LCD Backlight Enable */ + MX28_PAD_AUART0_CTS__GPIO_3_2 | (MXS_PAD_3V3 | MXS_PAD_4MA), + + /* LCD Brightness */ + MX28_PAD_PWM3__PWM_3 | MUX_CONFIG_PWM, + + /* Display On */ + MX28_PAD_GPMI_CE3N__GPIO_0_19 | MUX_CONFIG_GPIO, + + /* DUART with GPIO CTS Control - RS232 DEBUG Port */ + MX28_PAD_I2C0_SDA__DUART_TX | MUX_CONFIG_UART, + MX28_PAD_I2C0_SCL__DUART_RX | MUX_CONFIG_UART, + MX28_PAD_SSP0_DATA5__GPIO_2_5 | MUX_CONFIG_UART, + + /* AUART1 - RS232 */ + MX28_PAD_AUART1_RX__AUART1_RX | MUX_CONFIG_UART, + MX28_PAD_AUART1_TX__AUART1_TX | MUX_CONFIG_UART, + + /* AUART0 - RS485 */ + MX28_PAD_AUART0_RX__AUART0_RX | MUX_CONFIG_UART, + MX28_PAD_AUART0_TX__AUART0_TX | MUX_CONFIG_UART, + MX28_PAD_AUART0_RTS__AUART0_RTS | MUX_CONFIG_UART, + + /* AUART4 - RS485 */ + MX28_PAD_SAIF0_BITCLK__AUART4_RX | MUX_CONFIG_UART, + MX28_PAD_SAIF0_SDATA0__AUART4_TX | MUX_CONFIG_UART, + MX28_PAD_SAIF0_LRCLK__AUART4_RTS | MUX_CONFIG_UART, + + /* I2C */ + MX28_PAD_PWM0__I2C1_SCL | MUX_CONFIG_I2C, + MX28_PAD_PWM1__I2C1_SDA | MUX_CONFIG_I2C, + + /* CAN */ + MX28_PAD_GPMI_RDY2__CAN0_TX | MUX_CONFIG_CAN, + MX28_PAD_GPMI_RDY3__CAN0_RX | MUX_CONFIG_CAN, + + /* SPI */ + MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SPI, + MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SPI, + MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SPI, + MX28_PAD_SSP2_SS0__SSP2_D3 | MUX_CONFIG_SPI, + MX28_PAD_SSP2_SS1__SSP2_D4 | MUX_CONFIG_SPI, + + /* MMC0 */ + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0, + + /* GPIO Interrupt */ + MX28_PAD_GPMI_CE2N__GPIO_0_18 | MUX_CONFIG_GPIO, + + /* USB Reset */ + MX28_PAD_SSP0_DATA7__GPIO_2_7 | MUX_CONFIG_GPIO, + + /* USB Power Enable */ + MX28_PAD_SSP0_DATA4__GPIO_2_4 | MUX_CONFIG_GPIO, + + /* USB Overcurrent */ + MX28_PAD_SSP2_SS2__USB0_OVERCURRENT | (MXS_PAD_3V3 | MXS_PAD_4MA), + + /* USB OTG ID */ + MX28_PAD_PWM2__USB0_ID | (MXS_PAD_3V3 | MXS_PAD_4MA), + + /* Onboard Audio */ + MX28_PAD_SAIF1_SDATA0__PWM_7 | MUX_CONFIG_PWM, + MX28_PAD_PWM4__PWM_4 | MUX_CONFIG_PWM, + + /* GPMI NAND */ + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CE1N__GPMI_CE1N | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDY1__GPMI_READY1 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDN__GPMI_RDN | (MXS_PAD_3V3 | + MXS_PAD_8MA | + MXS_PAD_PULLUP), + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, + + /* NAND WP */ + MX28_PAD_GPMI_RESETN__GPIO_0_28 | MUX_CONFIG_GPIO, + + /* FEC Ethernet */ + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + + /* PHY reset */ + MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_ENET, + + /* Ethernet Interrupt */ + MX28_PAD_SSP0_DATA6__GPIO_2_6 | MUX_CONFIG_ENET, + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, +}; + +void board_init_ll(const uint32_t arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} diff --git a/configs/g2c1_mmc_defconfig b/configs/g2c1_mmc_defconfig new file mode 100644 index 0000000..9ec2379 --- /dev/null +++ b/configs/g2c1_mmc_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_G2C1=y diff --git a/configs/g2c1_nand_defconfig b/configs/g2c1_nand_defconfig new file mode 100644 index 0000000..443eeeb --- /dev/null +++ b/configs/g2c1_nand_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_G2C1=y diff --git a/include/configs/g2c1.h b/include/configs/g2c1.h new file mode 100644 index 0000000..ddc12de --- /dev/null +++ b/include/configs/g2c1.h @@ -0,0 +1,307 @@ +/* + * Copyright (C) 2015 Graeme Russ gruss@tss-engineering.com + * on behalf of DENX Software Engineering GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIGS_G2C1_H__ +#define __CONFIGS_G2C1_H__ + +#ifdef DEBUG +#define CONFIG_SPL_SERIAL_SUPPORT +#endif + +/* System configurations */ +#define CONFIG_MX28 /* i.MX28 SoC */ +#define CONFIG_SYS_MXS_VDD5V_ONLY /* No Battery */ + +/* TODO: Remove all references to MACH_TYPE +#define MACH_TYPE_G2C1 3613 +#define CONFIG_MACH_TYPE MACH_TYPE_G2C1 +*/ + +#define CONFIG_FIT + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BMP +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_FUSE +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_CMD_USB +#define CONFIG_VIDEO + +#define CONFIG_REGEX /* Enable regular expression support */ + +/* Memory configuration */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Environment */ +#define CONFIG_ENV_SIZE (16 * 1024) + +#if defined(CONFIG_ENV_IS_IN_NAND) && defined(CONFIG_ENV_IS_IN_MMC) +#error "CONFIG_ENV_IS_IN_NAND and CONFIG_ENV_IS_IN_MMC cannot both be defined" +#elif defined(CONFIG_ENV_IS_IN_NAND) +/* Environment is in NAND - CONFIG_CMD_NAND must be defined*/ +#if !defined(CONFIG_CMD_NAND) +#define CONFIG_CMD_NAND +#endif +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_OFFSET (24 * CONFIG_ENV_SECT_SIZE) /* 3 MiB */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) +#elif defined(CONFIG_ENV_IS_IN_MMC) +/* Environment is in NAND - CONFIG_CMD_MMC must be defined*/ +#if !defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_MMC +#endif +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#else +#error "Either CONFIG_ENV_IS_IN_NAND or CONFIG_ENV_IS_IN_MMC must be defined" +#endif + +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nand0=gpmi-nand" +#define MTDPARTS_DEFAULT \ + "mtdparts=gpmi-nand:" \ + "3m(u-boot)," \ + "512k(env1)," \ + "512k(env2)," \ + "14m(boot)," \ + "238m(data)," \ + "-@4096k(UBI)" + +/* FEC Ethernet on SoC */ +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_PHYLIB +#define CONFIG_PHY_SMSC +#endif + +/* EEPROM */ +#ifdef CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#endif + +/* RTC */ +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_MXS +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_MXS_PORT0 +#define CONFIG_EHCI_MXS_PORT1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE +#endif + +/* SPI */ +#ifdef CONFIG_CMD_SPI +#define CONFIG_DEFAULT_SPI_BUS 2 +#define CONFIG_DEFAULT_SPI_CS 0 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 + +/* SPI FLASH */ +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SF_DEFAULT_BUS 2 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +#define CONFIG_ENV_SPI_BUS 2 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 40000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#endif + +#endif + +/* LCD */ +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) +#endif + +/* Booting Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "fitImage" +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " +#define CONFIG_BOOTCOMMAND "run mmc_mmc" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Extra Environment */ +#define CONFIG_PREBOOT "run try_bootscript" +#define CONFIG_HOSTNAME g2c1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "consdev=ttyAMA0\0" \ + "baudrate=115200\0" \ + "bootscript=boot.scr\0" \ + "bootdev=/dev/mmcblk0p2\0" \ + "rootdev=/dev/mmcblk0p3\0" \ + "netdev=eth0\0" \ + "hostname=g2c1\0" \ + "kernel_addr_r=0x42000000\0" \ + "videomode=video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066," \ + "le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296," \ + "vmode:0\0" \ + "update_nand_full_filename=u-boot.nand\0" \ + "update_nand_firmware_filename=u-boot.sb\0" \ + "update_sd_firmware_filename=u-boot.sd\0" \ + "update_nand_firmware_maxsz=0x100000\0" \ + "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ + "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ + "update_nand_get_fcb_size=" /* Get size of FCB blocks */ \ + "nand device 0 ; " \ + "nand info ; " \ + "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \ + "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \ + "update_nand_full=" /* Update FCB, DBBT and FW */ \ + "if tftp ${update_nand_full_filename} ; then " \ + "run update_nand_get_fcb_size ; " \ + "nand scrub -y 0x0 ${filesize} ; " \ + "nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \ + "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \ + "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \ + "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \ + "fi\0" \ + "update_nand_firmware=" /* Update only firmware */ \ + "if tftp ${update_nand_firmware_filename} ; then " \ + "run update_nand_get_fcb_size ; " \ + "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \ + "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \ + "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \ + "nand erase ${fcb_sz} ${fw_sz} ; " \ + "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ + "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ + "fi\0" \ + "update_sd_firmware=" /* Update the SD firmware partition */ \ + "if mmc rescan ; then " \ + "if tftp ${update_sd_firmware_filename} ; then " \ + "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ + "setexpr fw_sz ${fw_sz} + 1 ; " \ + "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ + "fi ; " \ + "fi\0" \ + "addcons=" \ + "setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "addip=" \ + "setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off\0" \ + "addmisc=" \ + "setenv bootargs ${bootargs} ${miscargs}\0" \ + "adddfltmtd=" \ + "if test "x${mtdparts}" == "x" ; then " \ + "mtdparts default ; " \ + "fi\0" \ + "addmtd=" \ + "run adddfltmtd ; " \ + "setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addargs=run addcons addmtd addmisc\0" \ + "mmcload=" \ + "mmc rescan ; " \ + "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \ + "ubiload=" \ + "ubi part UBI ; ubifsmount ubi0:rootfs ; " \ + "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ + "netload=" \ + "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ + "miscargs=nohlt panic=1\0" \ + "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ + "ubiargs=" \ + "setenv bootargs ubi.mtd=5 " \ + "root=ubi0:rootfs rootfstype=ubifs\0" \ + "nfsargs=" \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ + "mmc_mmc=" \ + "run mmcload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "mmc_ubi=" \ + "run mmcload ubiargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "mmc_nfs=" \ + "run mmcload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "ubi_mmc=" \ + "run ubiload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "ubi_ubi=" \ + "run ubiload ubiargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "ubi_nfs=" \ + "run ubiload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_mmc=" \ + "run netload mmcargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_ubi=" \ + "run netload ubiargs addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "net_nfs=" \ + "run netload nfsargs addip addargs ; " \ + "bootm ${kernel_addr_r}\0" \ + "try_bootscript=" \ + "mmc rescan;" \ + "if test -e mmc 0:2 ${bootscript} ; then " \ + "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \ + "then ; " \ + "echo Running bootscript... ; " \ + "source ${kernel_addr_r} ; " \ + "fi ; " \ + "fi\0" + +/* The rest of the configuration is shared */ +#include <configs/mxs.h> + +#endif /* __CONFIGS_G2C1_H__ */