Hi Andreas,
On 12/20/11 13:53, Andreas Müller wrote:
On Tuesday, December 20, 2011 12:41:08 PM you wrote:
Dear Tom Rini,
In message <CA+M6bXn_ZBqA8rosE4L4O+4Eu+grAhWgCZ=u=2Nomb6WcyL6-
w@mail.gmail.com> you wrote:
I guess you really, really must use i2c before relocation? =A0If possible, this should be avoided in the first place.
Yes, board rev detection to know how to configure SDRAM.
I don't consider this a valid reason (reading the SPD EEPROM would be such a reason). In almost all other cases it should be suffucient to configure the maximum number of memory banks and the maximum size of the memory banks and then use get_ram_size() to determine the actual amount of memory and to correctly initialize the memory controller.
Note that I don't insist on any changes to existing code here. This is just a recommendation which you may (or may not) consider for any future ports / implementations.
Dear Wolfgang Denk,
I agree to your concerns but - as I understood Steve Sakoman - here the situation is slightly different: At elder overo boards TWL4030 RTC irq is connected to gpio112. Unfortunately this pin is also used for binary revision detection. Therefore we need to send 'shut-up' to TWL4030 via i2c to avoid reading wrong revision. In SPL this must be done *before* SDRAM (timing) is set up, because the type of SDRAM is revision dependent.
What about forging some very not optimized default DRAM settings, that suit any assembled DRAM and then when you have I2C access, reconfigure it - is it possible?