Hi Marek,
Dear Detlev Zundel,
Hi Marek,
[...]
- Why was the change made in the first place and for what OOT port?
Change of a DRAM configuration register that enabled additional address bit, at address 512MB of DRAM. Though this caused memory hole on our M28 module with 256MB of DRAM, which _is_ mainline. X board is OOT and never will be mainlined I guess.
I still do not understand this fully. What exactly is this "memory hole" and why is it fatal? As far as I can remember, there are always some holes in the adress map, so why is this special?
No, this one created this layout on our 256 MB module:
[chunk of memory][<- same thing][chunk of memory][<- same thing]
so get_ram_size() didn't work with it and it actually overwrote part of the U- Boot etc.
Ah, so it created what I would call a "memory mirroring" or "memory aliasing", right? Now I understand the problem, thanks.
Cheers Detlev