
8 Aug
2017
8 Aug
'17
6:13 a.m.
On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng icenowy@aosc.io wrote:
Some new Allwinner SoCs' PRCM has a secure switch register, which controls the access to some clock and power registers in PRCM block.
Add the definition of this register and its bits in the PRCM header file.
Signed-off-by: Icenowy Zheng icenowy@aosc.io
Could you provide a reference as to where or how you found out about this?
Thanks ChenYu