From: Jerry Huang Chang-Ming.Huang@freescale.com
The new MPC8360EMDS board supports 512MB DDR since 2008.
For 512MB DDR: BAT0 is used for the first 256MB memory, BAT4 is used for the second 256MB memory and the address space of SDRAM follows the DDR, so if the size of DDR is 256MB, the BAT4 will be used for SDRAM and if the size of DDR is 512MB, the BAT4 will be used for the second 256MB memory and there is no BAT for SDRAM. Therefore, if the size of DDR is 512MB, this patch will use BAT6 for SDRAM and BAT5 will be used for PCI MEM to replace the BAT6 after the codes relocates to the DDR.
Signed-off-by: Jerry Huang Chang-Ming.Huang@freescale.com CC: Kim Phillips kim.phillips@freescale.com --- cahnges for v2: - fix multiline comment wrong changes for v3: - change the oscillator to 33330000, not 33300000 changes for v4: - add the mandatory history of changes changes for v5: - move the code to platform file from lib/board.c - add 2011 copyright changes for v6: - split into two patch - clean the code - add CC
board/freescale/mpc8360emds/mpc8360emds.c | 27 ++++++++++++++++++++++++++- include/configs/MPC8360EMDS.h | 3 ++- 2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 0babd26..f150a09 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006,2010 Freescale Semiconductor, Inc. + * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc. * Dave Liu daveliu@freescale.com * * See file CREDITS for list of people who contributed to this @@ -23,6 +23,7 @@ #include <asm/mmu.h> #include <asm/io.h> #include <asm/fsl_enet.h> +#include <asm/mmu.h> #if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> #endif @@ -138,9 +139,20 @@ int board_early_init_f(void)
int board_early_init_r(void) { + gd_t *gd; #ifdef CONFIG_PQ_MDS_PIB pib_init(); #endif + /* + * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB + * So re-setup PCI MEM space used BAT5 after relocated to DDR + */ + gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); + write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); + } + return 0; }
@@ -290,6 +302,19 @@ static int sdram_init(unsigned int base) if (rem) base = base - rem + sdram_size;
+ /* + * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB + * After relocated to DDR, reuse BAT5 for PCI MEM space + */ + if (base > CONFIG_MAX_MEM_MAPPED) { + unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE; + unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP; + + /* Setup the BAT6 for SDRAM */ + write_bat(DBAT6, batu, batl); + write_bat(IBAT6, batu, batl); + } + sdram_addr = (uint *)base; /* * Setup SDRAM Base and Option Registers diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index a959940..cfba894 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Copyright (C) 2006,2011 Freescale Semiconductor, Inc. * * Dave Liu daveliu@freescale.com * @@ -506,6 +506,7 @@ */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CONFIG_BAT_RW
/* DDR/LBC SDRAM: cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)