Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- Build tested only. Don't have access to this hardware.
board/imx31_phycore/config.mk | 1 - board/imx31_phycore/imx31_phycore.c | 22 ++++++++++++++-------- include/configs/imx31_phycore.h | 12 ++++++++++++ 3 files changed, 26 insertions(+), 9 deletions(-) delete mode 100644 board/imx31_phycore/config.mk
diff --git a/board/imx31_phycore/config.mk b/board/imx31_phycore/config.mk deleted file mode 100644 index 0131edf..0000000 --- a/board/imx31_phycore/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x87f00000 diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c index 82daaa3..87b04d9 100644 --- a/board/imx31_phycore/imx31_phycore.c +++ b/board/imx31_phycore/imx31_phycore.c @@ -30,15 +30,24 @@
DECLARE_GLOBAL_DATA_PTR;
-int dram_init (void) +int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + return 0; +} + +int board_init(void) +{ + + gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ + gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
return 0; }
-int board_init (void) +int board_early_init_f(void) { __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ __REG(CSCR_L(0)) = 0x10000d03; @@ -61,10 +70,7 @@ int board_init (void) /* setup pins for I2C2 (for EEPROM, RTC) */ mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL); mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA); - - gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ - gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ - + return 0; }
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 4d11f97..a0c0f1b 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -28,6 +28,8 @@ #ifndef __CONFIG_H #define __CONFIG_H
+#include <asm/arch/imx-regs.h> + /* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_MX31 1 /* in a mx31 */ @@ -143,6 +145,16 @@ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SYS_TEXT_BASE 0xA0000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_GBL_DATA_OFFSET)
/*----------------------------------------------------------------------- * FLASH and environment organization