Hi Fabio,
On 05/17/2017 11:08 PM, Fabio Estevam wrote:
Hi Hector,
On Wed, May 17, 2017 at 5:50 AM, Palacios, Hector Hector.Palacios@digi.com wrote:
The code is on Github [1] (well, not the dual-die DDR3 yet) but there isn't much to see for this issue other than:
I looked at your code and I see:
int dram_init(void) { gd->ram_size = ((ulong)CONFIG_DDR_MB * SZ_1M);
return 0; }
which may be worth investigating.
Take a look in this same function at board/freescale/mx53loco/mx53loco.c and also in include/configs/mx53loco.h (hint: we pass #define CONFIG_NR_DRAM_BANKS 2).
In case I wasn't clear, I don't have any memory mapping problems. I have one single DDR chip, which internally uses two dies and two chip selects. Setting CONFIG_NR_DRAM_BANKS to 1 (and full size) or 2 (and half size) in U-Boot doesn't make any difference in terms of performance.
Additional investigation showed the following:
NXP DDR stress test takes the same time to complete (successfully) in both variants (single-die with one chip select and 1GB density per CS, and dual-die with two chip select and 512MB per CS)
The slow memory access is global in U-Boot, not limited to 'mtest' command. A memory copy command for 256M (time cp.l 90000000 80000000 4000000) takes: - 1.304s on the single-die DDR3 - 15.866 seconds on the dual-die DDR3
Note that both data/instuction cache are ON on both devices, and that I'm only exercising the lower memory (only CS0 on the dual-die chip) to avoid potential issues or delays between changing from CS0 to CS1.
I also verified that configuring the MMDC0 for using only one CS on the dual-die DDR3 chip (and only half the size), does not help. This DDR is still performing slowly in U-Boot, but I can't find the reason why.
Thanks for your help, anyway. -- Hector Palacios