Testing shows, that PHY polling needs to be enabled on Armada 7k/8k. Otherwise ethernet transfers will not work correctly. PHY polling is enabled per default after reset, so we do not need to specifically enable it, but this makes it clearer.
Signed-off-by: Stefan Roese sr@denx.de Cc: Stefan Chulski stefanc@marvell.com Cc: Kostya Porotchkin kostap@marvell.com Cc: Nadav Haklai nadavh@marvell.com ---
drivers/net/mvpp2.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c index c940b95d05..6537ee3f92 100644 --- a/drivers/net/mvpp2.c +++ b/drivers/net/mvpp2.c @@ -5159,14 +5159,15 @@ static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv) if (priv->hw_version == MVPP22) mvpp2_axi_init(priv);
- /* Disable HW PHY polling */ if (priv->hw_version == MVPP21) { + /* Disable HW PHY polling */ val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); val |= MVPP2_PHY_AN_STOP_SMI0_MASK; writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); } else { + /* Enable HW PHY polling */ val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); - val &= ~MVPP22_SMI_POLLING_EN; + val |= MVPP22_SMI_POLLING_EN; writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); }