Hi Matthias,
I noticed some strange issues with our PMC440 (PPC440PEx based) board and also with the sequoia eval platform.
In a certain configuration these boards stuck during the Ethernet POST tests. When they got stuck, it is even not possible to attach with a BDI2000.
Oh, this hints to some deeper problems, so maybe one should check all erratas (again).
On the console you only see this:
U-Boot 1.3.1 (May 30 2008 - 17:01:42)
CPU: AMCC PowerPC 440EPx Rev. A at 533.333 MHz (PLB=133, OPB=66, EBC=66 MHz) Security/Kasumi support Bootstrap Option H - Boot ROM Location I2C (Addr 0x52) Internal PCI arbiter enabled, PCI async ext clock used 32 kB I-Cache 32 kB D-Cache Board: Sequoia - AMCC PPC440EPx Evaluation Board, Rev. F, PCI=33 MHz I2C: ready DTT: 1 is 38 C DRAM: 256 MB FLASH: 64 MB NAND: 32 MiB PCI: Bus Dev VenId DevId Class Int 00 0c 168c 0013 0200 43 In: serial Out: serial Err: serial USB: Host(int phy) Device(ext phy) Net: ppc_4xx_eth0, ppc_4xx_eth1
[...]
Did anybody else see this behavior?
The last time I had problems looking similar to what you see, these two commits from Anatolij solved my problems:
commit 5e3dca577b7c1bf58bd2b48449b18b7e7dcd8e04 Author: Anatolij Gustschin agust@denx.de Date: Thu Apr 17 18:18:00 2008 +0200
Fix crash on sequoia in ppc_4xx_eth_init
Currently U-Boot crashes in ppc_4xx_eth_init on sequoia with cache enabled (TLB Parity exeption). This patch fixes the problem.
Signed-off-by: Anatolij Gustschin agust@denx.de
commit accf7355767dc7f6b85d88bb1c75c9d95e84ba5b Author: Anatolij Gustschin agust@denx.de Date: Thu Apr 17 18:15:27 2008 +0200
ppc4xx: Fix crash on sequoia with cache enabled
Currently U-Boot crashes on sequoia board in CPU POST if cache is enabled (CONFIG_4xx_DCACHE defined). The cache won't be disabled by change_tlb before CPU POST because there is an insufficient adress range check since CFG_MEM_TOP_HIDE was introduced. This patch tries to fix this problem.
Signed-off-by: Anatolij Gustschin agust@denx.de
Cheers Detlev