Added FU540 place-holder so that SoC specific values will be kept here.
Signed-off-by: Pragnesh Patel pragnesh.patel@sifive.com --- arch/riscv/include/asm/arch-fu540/clk.h | 14 ++++++++ arch/riscv/include/asm/arch-fu540/gpio.h | 42 ++++++++++++++++++++++ arch/riscv/include/asm/arch-generic/gpio.h | 32 ++--------------- board/sifive/fu540/Kconfig | 3 ++ 4 files changed, 62 insertions(+), 29 deletions(-) create mode 100644 arch/riscv/include/asm/arch-fu540/clk.h create mode 100644 arch/riscv/include/asm/arch-fu540/gpio.h
diff --git a/arch/riscv/include/asm/arch-fu540/clk.h b/arch/riscv/include/asm/arch-fu540/clk.h new file mode 100644 index 0000000000..b39f5b55c9 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/clk.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 SiFive, Inc. + * + * Authors: + * Pragnesh Patel pragnesh.patel@sifive.com + */ + +#ifndef _CLK_FU540_H +#define _CLK_FU540_H + +/* Note: This is a placeholder header for driver compilation. */ + +#endif diff --git a/arch/riscv/include/asm/arch-fu540/gpio.h b/arch/riscv/include/asm/arch-fu540/gpio.h new file mode 100644 index 0000000000..f8ddd75852 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/gpio.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 SiFive, Inc. + * + * Authors: + * Sagar Shrikant Kadam sagar.kadam@sifive.com + */ + +#ifndef _GPIO_FU540_H +#define _GPIO_FU540_H + +#define GPIO_INPUT_VAL (0x00) +#define GPIO_INPUT_EN (0x04) +#define GPIO_OUTPUT_EN (0x08) +#define GPIO_OUTPUT_VAL (0x0C) +#define GPIO_PULLUP_EN (0x10) +#define GPIO_DRIVE (0x14) +#define GPIO_RISE_IE (0x18) +#define GPIO_RISE_IP (0x1C) +#define GPIO_FALL_IE (0x20) +#define GPIO_FALL_IP (0x24) +#define GPIO_HIGH_IE (0x28) +#define GPIO_HIGH_IP (0x2C) +#define GPIO_LOW_IE (0x30) +#define GPIO_LOW_IP (0x34) +#define GPIO_IOF_EN (0x38) +#define GPIO_IOF_SEL (0x3C) +#define GPIO_OUTPUT_XOR (0x40) + +#define NR_GPIOS 16 + +enum gpio_state { + LOW, + HIGH +}; + +/* Details about a GPIO bank */ +struct sifive_gpio_platdata { + void *base; /* address of registers in physical memory */ +}; + +#endif /* _GPIO_FU540_H */ diff --git a/arch/riscv/include/asm/arch-generic/gpio.h b/arch/riscv/include/asm/arch-generic/gpio.h index dfcb753051..5f0dc0a801 100644 --- a/arch/riscv/include/asm/arch-generic/gpio.h +++ b/arch/riscv/include/asm/arch-generic/gpio.h @@ -3,33 +3,7 @@ * Copyright (C) 2019 SiFive, Inc. */
-#ifndef _GPIO_SIFIVE_H -#define _GPIO_SIFIVE_H +#ifndef __ASM_RISCV_ARCH_GPIO_H +#define __ASM_RISCV_ARCH_GPIO_H
-#define GPIO_INPUT_VAL 0x00 -#define GPIO_INPUT_EN 0x04 -#define GPIO_OUTPUT_EN 0x08 -#define GPIO_OUTPUT_VAL 0x0C -#define GPIO_RISE_IE 0x18 -#define GPIO_RISE_IP 0x1C -#define GPIO_FALL_IE 0x20 -#define GPIO_FALL_IP 0x24 -#define GPIO_HIGH_IE 0x28 -#define GPIO_HIGH_IP 0x2C -#define GPIO_LOW_IE 0x30 -#define GPIO_LOW_IP 0x34 -#define GPIO_OUTPUT_XOR 0x40 - -#define NR_GPIOS 16 - -enum gpio_state { - LOW, - HIGH -}; - -/* Details about a GPIO bank */ -struct sifive_gpio_platdata { - void *base; /* address of registers in physical memory */ -}; - -#endif /* _GPIO_SIFIVE_H */ +#endif /* __ASM_RISCV_ARCH_GPIO_H */ diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index 5ca21474de..816a135b21 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -12,6 +12,9 @@ config SYS_CPU config SYS_CONFIG_NAME default "sifive-fu540"
+config SYS_SOC + default "fu540" + config SYS_TEXT_BASE default 0x80000000 if !RISCV_SMODE default 0x80200000 if RISCV_SMODE