8 Oct
2016
8 Oct
'16
7:14 p.m.
On 08/08/2016 12:18 AM, yuantian.tang@nxp.com wrote:
From: Tang Yuantian Yuantian.Tang@nxp.com
By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes.
Signed-off-by: Tang Yuantian yuantian.tang@nxp.com
Applied to fsl-qoriq master, awaiting upstream. Thanks.
York