12 May
2020
12 May
'20
6:46 p.m.
On Tue, May 12, 2020 at 12:42 PM Sylwester Nawrocki s.nawrocki@samsung.com wrote:
Hi Jim,
On 08.05.2020 16:25, Jim Quinlan wrote:
static int brcm_pcie_probe(struct udevice *dev) +{
struct udevice *ctlr = pci_get_controller(dev);struct pci_controller *hose = dev_get_uclass_priv(ctlr);struct brcm_pcie *pcie = dev_get_priv(dev);void __iomem *base = pcie->base;bool ssc_good = false;int num_out_wins = 0;u64 rc_bar2_offset, rc_bar2_size;unsigned int scb_size_val;int i, ret;u16 nlw, cls, lnksta;u32 tmp;/* Reset the bridge */brcm_pcie_bridge_sw_init_set(pcie, 1);udelay(150);Please add a comment as to how you chose the value, and below.
This was picked from Jim Quinlan's original code submission: https://protect2.fireeye.com/url?k=9d9c41ed-c002ef77-9d9dcaa2-0cc47a336fae-2...
Sadly there isn't any comment there.
The bridge is being reset and then un-reset. The delay is a safety precaution to preclude the reset signal from looking like a glitch.
If you don't mind I will add that sentence as a comment for the reset delay.
Yes, please do. Thanks, Jim
-- Regards, Sylwester