
On AT91 the watchdog mode register can only be written once after reset. If this register is written by u-boot e.g. a Linux driver can't reconfigure the watchdog later. If the watchdog is left untouched this is possible. Without touching the mode register the watchdog has a default setup and u-boot is still able to trigger the watchdog.
Signed-off-by: Alexander Stein alexander.stein@systec-electronic.com --- Changes in v2: * Add a new specific option CONFIG_SKIP_WATCHDOG_INIT * Add some documentation
Changes in v3: * Be more verbose in describing the problem in the commit message and README
Changes in v4: * Fix commit message
README | 11 +++++++++++ arch/arm/cpu/arm926ejs/at91/lowlevel_init.S | 2 ++ 2 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/README b/README index b6bf451..9fbb6c9 100644 --- a/README +++ b/README @@ -2827,6 +2827,17 @@ Low Level (hardware related) configuration options: some other boot loader or by a debugger which performs these initializations itself.
+- CONFIG_SKIP_WATCHDOG_INIT + + [arm AT91 only] If this variable is defined, then the + watchdog will not be programmed upon u-boot start. + On AT91 the watchdog mode register can only be written + once after reset. If this register is written by u-boot + e.g. a Linux driver can't reconfigure the watchdog later. If + the watchdog is left untouched this is possible. + Without touching the mode register the watchdog has a default + setup and u-boot is still able to trigger the watchdog. + - CONFIG_PRELOADER
Modifies the behaviour of start.S when compiling a loader diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S index 559c35c..0645ba8 100644 --- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S @@ -186,8 +186,10 @@ SDRAM_setup_end: .ltorg
SMRDATA: +#ifndef CONFIG_SKIP_WATCHDOG_INIT .word AT91_ASM_WDT_MR .word CONFIG_SYS_WDTC_WDMR_VAL +#endif /* configure PIOx as EBI0 D[16-31] */ #if defined(CONFIG_AT91SAM9263) .word AT91_ASM_PIOD_PDR