Convert register access to structure style, part #2.
No functional change.
Signed-off-by: Jason Kridner jkridner@gmail.com Signed-off-by: Dirk Behme dirk.behme@googlemail.com
--- board/omap3/beagle/beagle.c | 16 +---- board/omap3/evm/evm.c | 39 +++++------- board/omap3/overo/overo.c | 16 +---- board/omap3/pandora/pandora.c | 21 +++--- cpu/arm_cortexa8/omap3/interrupts.c | 10 +-- cpu/arm_cortexa8/omap3/mem.c | 105 +++++++++++++++++---------------- cpu/arm_cortexa8/omap3/sys_info.c | 22 +++--- cpu/arm_cortexa8/omap3/syslib.c | 11 +-- drivers/mtd/nand/omap_gpmc.c | 47 +++++++------- include/asm-arm/arch-omap3/mem.h | 9 +- include/asm-arm/arch-omap3/omap3.h | 22 +++++- include/asm-arm/arch-omap3/sys_proto.h | 4 - include/configs/omap3_beagle.h | 17 +++-- include/configs/omap3_evm.h | 18 +++-- include/configs/omap3_overo.h | 17 +++-- include/configs/omap3_pandora.h | 17 +++-- 16 files changed, 204 insertions(+), 187 deletions(-)
Index: u-boot-arm/cpu/arm_cortexa8/omap3/interrupts.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/interrupts.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/interrupts.c @@ -167,16 +167,16 @@ void do_irq(struct pt_regs *pt_regs)
static ulong timestamp; static ulong lastinc; -static u32 *timer_base = (u32 *)CONFIG_SYS_TIMERBASE; +static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
/* nothing really to do with interrupts, just starts up a counter. */ int interrupt_init(void) { /* start the counter ticking up, reload value on overflow */ - writel(TIMER_LOAD_VAL, timer_base + OFFS(TLDR)); + writel(TIMER_LOAD_VAL, &timer_base->tldr); /* enable timer */ writel((CONFIG_SYS_PVT << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, - timer_base + OFFS(TCLR)); + &timer_base->tclr);
reset_timer_masked(); /* init the timestamp and lastinc value */
@@ -232,13 +232,13 @@ void udelay(unsigned long usec) void reset_timer_masked(void) { /* reset time, capture current incrementer value time */ - lastinc = readl(timer_base + OFFS(TCRR)); + lastinc = readl(&timer_base->tcrr); timestamp = 0; /* start "advancing" time stamp from 0 */ }
ulong get_timer_masked(void) { - ulong now = readl(timer_base + OFFS(TCRR)); /* current tick value */ + ulong now = readl(&timer_base->tcrr); /* current tick value */
if (now >= lastinc) /* normal mode (non roll) */ /* move stamp fordward with absoulte diff ticks */ Index: u-boot-arm/drivers/mtd/nand/omap_gpmc.c =================================================================== --- u-boot-arm.orig/drivers/mtd/nand/omap_gpmc.c +++ u-boot-arm/drivers/mtd/nand/omap_gpmc.c @@ -30,8 +30,8 @@ #include <nand.h>
static uint8_t cs; -static uint32_t *gpmc_base = (uint32_t *)GPMC_BASE; -static uint32_t *gpmc_cs_base; +static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE; +static gpmc_csx_t *gpmc_cs_base; static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
/* @@ -49,13 +49,13 @@ static void omap_nand_hwcontrol(struct m */ switch (ctrl) { case NAND_CTRL_CHANGE | NAND_CTRL_CLE: - this->IO_ADDR_W = gpmc_cs_base + OFFS(GPMC_NAND_CMD); + this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_cmd; break; case NAND_CTRL_CHANGE | NAND_CTRL_ALE: - this->IO_ADDR_W = gpmc_cs_base + OFFS(GPMC_NAND_ADR); + this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_adr; break; case NAND_CTRL_CHANGE | NAND_NCE: - this->IO_ADDR_W = gpmc_cs_base + OFFS(GPMC_NAND_DAT); + this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_dat; break; }
@@ -75,9 +75,8 @@ static void omap_hwecc_init(struct nand_ * Init ECC Control Register * Clear all ECC | Enable Reg1 */ - writel(ECCCLEAR | ECCRESULTREG1, gpmc_base + OFFS(GPMC_ECC_CONTROL)); - writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, - gpmc_base + OFFS(GPMC_ECC_SIZE_CONFIG)); + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control); + writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_base->ecc_size_config); }
/* @@ -109,7 +108,7 @@ static uint32_t gen_true_ecc(uint8_t *ec * @return 0 if data is OK or corrected, else returns -1 */ static int omap_correct_data(struct mtd_info *mtd, uint8_t *dat, - uint8_t *read_ecc, uint8_t *calc_ecc) + uint8_t *read_ecc, uint8_t *calc_ecc) { uint32_t orig_ecc, new_ecc, res, hm; uint16_t parity_bits, byte; @@ -175,12 +174,12 @@ static int omap_correct_data(struct mtd_ * @ecc_code: ecc_code buffer */ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, - uint8_t *ecc_code) + uint8_t *ecc_code) { u_int32_t val;
/* Start Reading from HW ECC1_Result = 0x200 */ - val = readl(gpmc_base + OFFS(GPMC_ECC1_RESULT)); + val = readl(&gpmc_base->ecc1_result);
ecc_code[0] = val & 0xFF; ecc_code[1] = (val >> 16) & 0xFF; @@ -190,7 +189,7 @@ static int omap_calculate_ecc(struct mtd * Stop reading anymore ECC vals and clear old results * enable will be called if more reads are required */ - writel(0x000, gpmc_base + OFFS(GPMC_ECC_CONFIG)); + writel(0x000, &gpmc_base->ecc_config);
return 0; } @@ -209,17 +208,17 @@ static void omap_enable_hwecc(struct mtd case NAND_ECC_READ: case NAND_ECC_WRITE: /* Clear the ecc result registers, select ecc reg as 1 */ - writel(ECCCLEAR | ECCRESULTREG1, - gpmc_base + OFFS(GPMC_ECC_CONTROL)); + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control); + /* * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes * tell all regs to generate size0 sized regs * we just have a single ECC engine for all CS */ writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, - gpmc_base + OFFS(GPMC_ECC_SIZE_CONFIG)); + &gpmc_base->ecc_size_config); val = (dev_width << 7) | (cs << 1) | (0x1); - writel(val, gpmc_base + OFFS(GPMC_ECC_CONFIG)); + writel(val, &gpmc_base->ecc_config); break; default: printf("Error: Unrecognized Mode[%d]!\n", mode); @@ -318,10 +317,10 @@ int board_nand_init(struct nand_chip *na * Each GPMC set for a single CS is at offset 0x30 * - already remapped for us */ - gpmc_cs_base = (void __iomem *)(GPMC_CONFIG_CS0_BASE + - (cs * GPMC_CONFIG_WIDTH)); + gpmc_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE + + (cs * GPMC_CONFIG_WIDTH)); /* Check if NAND type is set */ - if ((readl(gpmc_cs_base + OFFS(GPMC_CONFIG1)) & 0xC00) == + if ((readl(&gpmc_cs_base->config1) & 0xC00) == 0x800) { /* Found it!! */ break; @@ -330,17 +329,17 @@ int board_nand_init(struct nand_chip *na } if (cs >= GPMC_MAX_CS) { printf("NAND: Unable to find NAND settings in " - "GPMC Configuration - quitting\n"); + "GPMC Configuration - quitting\n"); return -ENODEV; }
- gpmc_config = readl(gpmc_base + OFFS(GPMC_CONFIG)); + gpmc_config = readl(&gpmc_base->config); /* Disable Write protect */ gpmc_config |= 0x10; - writel(gpmc_config, gpmc_base + OFFS(GPMC_CONFIG)); + writel(gpmc_config, &gpmc_base->config);
- nand->IO_ADDR_R = gpmc_cs_base + OFFS(GPMC_NAND_DAT); - nand->IO_ADDR_W = gpmc_cs_base + OFFS(GPMC_NAND_CMD); + nand->IO_ADDR_R = (void __iomem *)&gpmc_cs_base->nand_dat; + nand->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_cmd;
nand->cmd_ctrl = omap_nand_hwcontrol; nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR | Index: u-boot-arm/cpu/arm_cortexa8/omap3/sys_info.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/sys_info.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/sys_info.c @@ -32,9 +32,9 @@ #include <i2c.h>
extern omap3_sysinfo sysinfo; -static u32 *gpmc_base = (u32 *)GPMC_BASE; -static u32 *sdrc_base = (u32 *)OMAP34XX_SDRC_BASE; -static u32 *ctrl_base = (u32 *)OMAP34XX_CTRL_BASE; +static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE; +static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE; +static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
/****************************************** * get_cpu_rev(void) - extract version info @@ -61,8 +61,7 @@ u32 get_cpu_rev(void) ****************************************************/ u32 is_mem_sdr(void) { - if (readl(sdrc_base + OFFS(SDRC_MR_0 + SDRC_CS0_OSET)) == - SDP_SDRC_MR_0_SDR) + if (readl(&sdrc_base->cs[CS0].mr) == SDP_SDRC_MR_0_SDR) return 1; return 0; } @@ -70,12 +69,12 @@ u32 is_mem_sdr(void) /*********************************************************************** * get_cs0_size() - get size of chip select 0/1 ************************************************************************/ -u32 get_sdr_cs_size(u32 offset) +u32 get_sdr_cs_size(u32 cs) { u32 size;
/* get ram size field */ - size = readl(sdrc_base + OFFS(SDRC_MCFG_0 + offset)) >> 8; + size = readl(&sdrc_base->cs[cs].mcfg) >> 8; size &= 0x3FF; /* remove unwanted bits */ size *= SZ_2M; /* find size in MB */ return size; @@ -91,7 +90,7 @@ u32 get_sdr_cs_offset(u32 cs) if (!cs) return 0;
- offset = readl(sdrc_base + OFFS(SDRC_CS_CFG)); + offset = readl(&sdrc_base->cs_cfg); offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
return offset; @@ -129,7 +128,7 @@ u32 get_gpmc0_base(void) { u32 b;
- b = readl(gpmc_base + OFFS(GPMC_CONFIG7)); + b = readl(&gpmc_cs_base->config7); b &= 0x1F; /* keep base [5:0] */ b = b << 24; /* ret 0x0b000000 */ return b; @@ -243,7 +242,7 @@ u32 is_running_in_sdram(void) ***************************************************************/ u32 get_boot_type(void) { - return (readl(ctrl_base + OFFS(CONTROL_STATUS)) & SYSBOOT_MASK); + return (readl(&ctrl_base->status) & SYSBOOT_MASK); }
/************************************************************* @@ -251,6 +250,5 @@ u32 get_boot_type(void) *************************************************************/ u32 get_device_type(void) { - return ((readl(ctrl_base + OFFS(CONTROL_STATUS)) & - (DEVICE_MASK)) >> 8); + return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8); } Index: u-boot-arm/cpu/arm_cortexa8/omap3/mem.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/mem.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/mem.c @@ -76,7 +76,8 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG6, 0 };
-u32 *nand_cs_base; +gpmc_csx_t *nand_cs_base; +gpmc_t *gpmc_cfg_base;
#if defined(CONFIG_ENV_IS_IN_NAND) #define GPMC_CS 0 @@ -96,7 +97,7 @@ static u32 gpmc_onenand[GPMC_MAX_REG] = ONENAND_GPMC_CONFIG6, 0 };
-u32 *onenand_cs_base; +gpmc_csx_t *onenand_cs_base;
#if defined(CONFIG_ENV_IS_IN_ONENAND) #define GPMC_CS 0 @@ -106,7 +107,7 @@ u32 *onenand_cs_base;
#endif
-static u32 *sdrc_base = (u32 *)OMAP34XX_SDRC_BASE; +static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
/************************************************************************** * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow @@ -118,11 +119,11 @@ void make_cs1_contiguous(void) { u32 size, a_add_low, a_add_high;
- size = get_sdr_cs_size(SDRC_CS0_OSET); + size = get_sdr_cs_size(CS0); size /= SZ_32M; /* find size to offset CS1 */ a_add_high = (size & 3) << 8; /* set up low field */ a_add_low = (size & 0x3C) >> 2; /* set up high field */ - writel((a_add_high | a_add_low), sdrc_base + OFFS(SDRC_CS_CFG)); + writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
}
@@ -158,7 +159,7 @@ u32 mem_ok(u32 cs) void sdrc_init(void) { /* only init up first bank here */ - do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); + do_sdrc_init(CS0, EARLY_INIT); }
/************************************************************************* @@ -167,70 +168,73 @@ void sdrc_init(void) * -optimal settings can be placed here, or redone after i2c * inspection of board info * - * - code called ones in C-Stack only context for CS0 and a possible 2nd + * - code called once in C-Stack only context for CS0 and a possible 2nd * time depending on memory configuration from stack+global context **************************************************************************/
-void do_sdrc_init(u32 offset, u32 early) +void do_sdrc_init(u32 cs, u32 early) { - u32 actim_offs = offset? 0x28: 0; + sdrc_actim_t *sdrc_actim_base; + + if(cs) + sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL1_BASE; + else + sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL0_BASE;
if (early) { /* reset sdrc controller */ - writel(SOFTRESET, sdrc_base + OFFS(SDRC_SYSCONFIG)); - wait_on_value(RESETDONE, RESETDONE, SDRC_STATUS_REG, 12000000); - writel(0, sdrc_base + OFFS(SDRC_SYSCONFIG)); + writel(SOFTRESET, &sdrc_base->sysconfig); + wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status, + 12000000); + writel(0, &sdrc_base->sysconfig);
/* setup sdrc to ball mux */ - writel(SDP_SDRC_SHARING, sdrc_base + OFFS(SDRC_SHARING)); + writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
/* Disable Power Down of CKE cuz of 1 CKE on combo part */ - writel(SRFRONRESET | PAGEPOLICY_HIGH, - sdrc_base + OFFS(SDRC_POWER)); + writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
- writel(ENADLL | DLLPHASE_90, sdrc_base + OFFS(SDRC_DLLA_CTRL)); + writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000); }
writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY | RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 | - DEEPPD | DDR_SDRAM, sdrc_base + OFFS(SDRC_MCFG_0 + offset)); - writel(ARCV | ARE_ARCV_1, sdrc_base + OFFS(SDRC_RFR_CTRL + offset)); - writel(V_ACTIMA_165, sdrc_base + - OFFS(SDRC_ACTIM_CTRLA_0 + actim_offs)); - writel(V_ACTIMB_165, sdrc_base + - OFFS(SDRC_ACTIM_CTRLB_0 + actim_offs)); - - writel(CMD_NOP, sdrc_base + OFFS(SDRC_MANUAL_0 + offset)); - writel(CMD_PRECHARGE, sdrc_base + OFFS(SDRC_MANUAL_0 + offset)); - writel(CMD_AUTOREFRESH, sdrc_base + OFFS(SDRC_MANUAL_0 + offset)); - writel(CMD_AUTOREFRESH, sdrc_base + OFFS(SDRC_MANUAL_0 + offset)); + DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg); + writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl); + writel(V_ACTIMA_165, &sdrc_actim_base->ctrla); + writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb); + + writel(CMD_NOP, &sdrc_base ->cs[cs].manual); + writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
/* * CAS latency 3, Write Burst = Read Burst, Serial Mode, * Burst length = 4 */ - writel(CASL3 | BURSTLENGTH4, sdrc_base + OFFS(SDRC_MR_0 + offset)); + writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
- if (!mem_ok(offset)) - writel(0, sdrc_base + OFFS(SDRC_MCFG_0 + offset)); + if (!mem_ok(cs)) + writel(0, &sdrc_base->cs[cs].mcfg); }
-void enable_gpmc_config(u32 *gpmc_config, u32 *gpmc_cs_base, u32 base, +void enable_gpmc_config(u32 *gpmc_config, gpmc_csx_t *gpmc_cs_base, u32 base, u32 size) { - writel(0, gpmc_cs_base + OFFS(GPMC_CONFIG7)); + writel(0, &gpmc_cs_base->config7); sdelay(1000); /* Delay for settling */ - writel(gpmc_config[0], gpmc_cs_base + OFFS(GPMC_CONFIG1)); - writel(gpmc_config[1], gpmc_cs_base + OFFS(GPMC_CONFIG2)); - writel(gpmc_config[2], gpmc_cs_base + OFFS(GPMC_CONFIG3)); - writel(gpmc_config[3], gpmc_cs_base + OFFS(GPMC_CONFIG4)); - writel(gpmc_config[4], gpmc_cs_base + OFFS(GPMC_CONFIG5)); - writel(gpmc_config[5], gpmc_cs_base + OFFS(GPMC_CONFIG6)); + writel(gpmc_config[0], &gpmc_cs_base->config1); + writel(gpmc_config[1], &gpmc_cs_base->config2); + writel(gpmc_config[2], &gpmc_cs_base->config3); + writel(gpmc_config[3], &gpmc_cs_base->config4); + writel(gpmc_config[4], &gpmc_cs_base->config5); + writel(gpmc_config[5], &gpmc_cs_base->config6); /* Enable the config */ writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | - (1 << 6)), gpmc_cs_base + OFFS(GPMC_CONFIG7)); + (1 << 6)), &gpmc_cs_base->config7); sdelay(2000); }
@@ -243,8 +247,8 @@ void gpmc_init(void) { /* putting a blanket check on GPMC based on ZeBu for now */ u32 *gpmc_config = NULL; - u32 *gpmc_base = (u32 *)GPMC_BASE; - u32 *gpmc_cs_base = (u32 *)GPMC_CONFIG_CS0_BASE; + gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE; + gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE; u32 base = 0; u32 size = 0; u32 f_off = CONFIG_SYS_MONITOR_LEN; @@ -252,24 +256,25 @@ void gpmc_init(void) u32 config = 0;
/* global settings */ - writel(0, gpmc_base + OFFS(GPMC_IRQENABLE)); /* isr's sources masked */ - writel(0, gpmc_base + OFFS(GPMC_TIMEOUT_CONTROL));/* timeout disable */ + writel(0, &gpmc_base->irqenable); /* isr's sources masked */ + writel(0, &gpmc_base->timeout_control);/* timeout disable */
- config = readl(gpmc_base + OFFS(GPMC_CONFIG)); + config = readl(&gpmc_base->config); config &= (~0xf00); - writel(config, gpmc_base + OFFS(GPMC_CONFIG)); + writel(config, &gpmc_base->config);
/* * Disable the GPMC0 config set by ROM code * It conflicts with our MPDB (both at 0x08000000) */ - writel(0, gpmc_cs_base + OFFS(GPMC_CONFIG7)); + writel(0, &gpmc_cs_base->config7); sdelay(1000);
#if defined(CONFIG_CMD_NAND) /* CS 0 */ gpmc_config = gpmc_m_nand; - nand_cs_base = (u32 *)(GPMC_CONFIG_CS0_BASE + - (GPMC_CS * GPMC_CONFIG_WIDTH)); + gpmc_cfg_base = gpmc_base; + nand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE + + (GPMC_CS * GPMC_CONFIG_WIDTH)); base = PISMO1_NAND_BASE; size = PISMO1_NAND_SIZE; enable_gpmc_config(gpmc_config, nand_cs_base, base, size); @@ -287,8 +292,8 @@ void gpmc_init(void)
#if defined(CONFIG_CMD_ONENAND) gpmc_config = gpmc_onenand; - onenand_cs_base = (u32 *)(GPMC_CONFIG_CS0_BASE + - (GPMC_CS * GPMC_CONFIG_WIDTH)); + onenand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE + + (GPMC_CS * GPMC_CONFIG_WIDTH)); base = PISMO1_ONEN_BASE; size = PISMO1_ONEN_SIZE; enable_gpmc_config(gpmc_config, onenand_cs_base, base, size); Index: u-boot-arm/board/omap3/evm/evm.c =================================================================== --- u-boot-arm.orig/board/omap3/evm/evm.c +++ u-boot-arm/board/omap3/evm/evm.c @@ -89,38 +89,35 @@ void set_muxconf_regs(void) *****************************************************************************/ static void setup_net_chip(void) { - unsigned int *gpio3_base = (unsigned int *)OMAP34XX_GPIO3_BASE; - unsigned int *gpmc_cs6_base = (unsigned int *)GPMC_CONFIG_CS6_BASE; - unsigned short *ctrl_base = (unsigned short *)OMAP34XX_CTRL_BASE; + gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE; + gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE; + ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */ - writel(NET_GPMC_CONFIG1, gpmc_cs6_base + OFFS(GPMC_CONFIG1)); - writel(NET_GPMC_CONFIG2, gpmc_cs6_base + OFFS(GPMC_CONFIG2)); - writel(NET_GPMC_CONFIG3, gpmc_cs6_base + OFFS(GPMC_CONFIG3)); - writel(NET_GPMC_CONFIG4, gpmc_cs6_base + OFFS(GPMC_CONFIG4)); - writel(NET_GPMC_CONFIG5, gpmc_cs6_base + OFFS(GPMC_CONFIG5)); - writel(NET_GPMC_CONFIG6, gpmc_cs6_base + OFFS(GPMC_CONFIG6)); - writel(NET_GPMC_CONFIG7, gpmc_cs6_base + OFFS(GPMC_CONFIG7)); + writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1); + writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2); + writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3); + writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4); + writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5); + writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6); + writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */ - writew(readw(ctrl_base + (CONTROL_PADCONF_GPMC_NWE >> 1)) | 0x0E00, - ctrl_base + (CONTROL_PADCONF_GPMC_NWE >> 1)); + writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(ctrl_base + (CONTROL_PADCONF_GPMC_NOE >> 1)) | 0x0E00, - ctrl_base + (CONTROL_PADCONF_GPMC_NOE >> 1)); + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ - writew(readw(ctrl_base + (CONTROL_PADCONF_GPMC_NADV_ALE >> 1)) | 0x0E00, - ctrl_base + (CONTROL_PADCONF_GPMC_NADV_ALE >> 1)); + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, + &ctrl_base->gpmc_nadv_ale);
/* Make GPIO 64 as output pin */ - writel(readl(gpio3_base + OFFS(GPIO_OE)) & ~(GPIO0), - gpio3_base + OFFS(GPIO_OE)); + writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe);
/* Now send a pulse on the GPIO pin */ - writel(GPIO0, gpio3_base + OFFS(GPIO_SETDATAOUT)); + writel(GPIO0, &gpio3_base->setdataout); udelay(1); - writel(GPIO0, gpio3_base + OFFS(GPIO_CLEARDATAOUT)); + writel(GPIO0, &gpio3_base->cleardataout); udelay(1); - writel(GPIO0, gpio3_base + OFFS(GPIO_SETDATAOUT)); + writel(GPIO0, &gpio3_base->setdataout); }
Index: u-boot-arm/include/configs/omap3_beagle.h =================================================================== --- u-boot-arm.orig/include/configs/omap3_beagle.h +++ u-boot-arm/include/configs/omap3_beagle.h @@ -285,7 +285,8 @@ #define ENV_IS_VARIABLE 1
#ifndef __ASSEMBLY__ -extern unsigned int *nand_cs_base; +extern gpmc_csx_t *nand_cs_base; +extern gpmc_t *gpmc_cfg_base; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; @@ -295,15 +296,17 @@ extern unsigned int boot_flash_type;
#define WRITE_NAND_COMMAND(d, adr)\ - writel(d, (nand_cs_base + OFFS(GPMC_NAND_CMD))) + writel(d, &nand_cs_base->nand_cmd) #define WRITE_NAND_ADDRESS(d, adr)\ - writel(d, (nand_cs_base + OFFS(GPMC_NAND_ADR))) -#define WRITE_NAND(d, adr) writew(d, (nand_cs_base + OFFS(GPMC_NAND_DAT))) -#define READ_NAND(adr) readl((nand_cs_base + OFFS(GPMC_NAND_DAT))) + writel(d, &nand_cs_base->nand_adr) +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
/* Other NAND Access APIs */ -#define NAND_WP_OFF() do {readl(GPMC_CONFIG_REG) |= GPMC_CONFIG_WP; } while (0) -#define NAND_WP_ON() do {readl(GPMC_CONFIG_REG) &= ~GPMC_CONFIG_WP; } while (0) +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ + while (0) +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ + while (0) #define NAND_DISABLE_CE(nand) #define NAND_ENABLE_CE(nand) #define NAND_WAIT_READY(nand) udelay(10) Index: u-boot-arm/include/configs/omap3_evm.h =================================================================== --- u-boot-arm.orig/include/configs/omap3_evm.h +++ u-boot-arm/include/configs/omap3_evm.h @@ -290,7 +290,8 @@ #define ENV_IS_VARIABLE 1
#ifndef __ASSEMBLY__ -extern unsigned int *nand_cs_base; +extern gpmc_csx_t *nand_cs_base; +extern gpmc_t *gpmc_cfg_base; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; @@ -300,20 +301,21 @@ extern unsigned int boot_flash_type;
#define WRITE_NAND_COMMAND(d, adr)\ - writel(d, (nand_cs_base + OFFS(GPMC_NAND_CMD))) + writel(d, &nand_cs_base->nand_cmd) #define WRITE_NAND_ADDRESS(d, adr)\ - writel(d, (nand_cs_base + OFFS(GPMC_NAND_ADR))) -#define WRITE_NAND(d, adr) writel(d, (nand_cs_base + OFFS(GPMC_NAND_DAT))) -#define READ_NAND(adr) readl((nand_cs_base + OFFS(GPMC_NAND_DAT))) + writel(d, &nand_cs_base->nand_adr) +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
/* Other NAND Access APIs */ -#define NAND_WP_OFF() do {readl(GPMC_CONFIG_REG) |= GPMC_CONFIG_WP; } while (0) -#define NAND_WP_ON() do {readl(GPMC_CONFIG_REG) &= ~GPMC_CONFIG_WP; } while (0) +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ + while (0) +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ + while (0) #define NAND_DISABLE_CE(nand) #define NAND_ENABLE_CE(nand) #define NAND_WAIT_READY(nand) udelay(10)
- /*---------------------------------------------------------------------------- * SMSC9115 Ethernet from SMSC9118 family *---------------------------------------------------------------------------- Index: u-boot-arm/include/configs/omap3_overo.h =================================================================== --- u-boot-arm.orig/include/configs/omap3_overo.h +++ u-boot-arm/include/configs/omap3_overo.h @@ -277,7 +277,8 @@ #define ENV_IS_VARIABLE 1
#ifndef __ASSEMBLY__ -extern unsigned int *nand_cs_base; +extern gpmc_csx_t *nand_cs_base; +extern gpmc_t *gpmc_cfg_base; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; @@ -287,15 +288,17 @@ extern unsigned int boot_flash_type;
#define WRITE_NAND_COMMAND(d, adr)\ - writel(d, (nand_cs_base + OFFS(GPMC_NAND_CMD))) + writel(d, &nand_cs_base->nand_cmd) #define WRITE_NAND_ADDRESS(d, adr)\ - writel(d, (nand_cs_base + OFFS(GPMC_NAND_ADR))) -#define WRITE_NAND(d, adr) writel(d, (nand_cs_base + OFFS(GPMC_NAND_DAT))) -#define READ_NAND(adr) readl((nand_cs_base + OFFS(GPMC_NAND_DAT))) + writel(d, &nand_cs_base->nand_adr) +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
/* Other NAND Access APIs */ -#define NAND_WP_OFF() do {readl(GPMC_CONFIG_REG) |= GPMC_CONFIG_WP; } while (0) -#define NAND_WP_ON() do {readl(GPMC_CONFIG_REG) &= ~GPMC_CONFIG_WP; } while (0) +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ + while (0) +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ + while (0) #define NAND_DISABLE_CE(nand) #define NAND_ENABLE_CE(nand) #define NAND_WAIT_READY(nand) udelay(10) Index: u-boot-arm/include/configs/omap3_pandora.h =================================================================== --- u-boot-arm.orig/include/configs/omap3_pandora.h +++ u-boot-arm/include/configs/omap3_pandora.h @@ -276,7 +276,8 @@ #define ENV_IS_VARIABLE 1
#ifndef __ASSEMBLY__ -extern unsigned int *nand_cs_base; +extern gpmc_csx_t *nand_cs_base; +extern gpmc_t *gpmc_cfg_base; extern unsigned int boot_flash_base; extern volatile unsigned int boot_flash_env_addr; extern unsigned int boot_flash_off; @@ -286,15 +287,17 @@ extern unsigned int boot_flash_type;
#define WRITE_NAND_COMMAND(d, adr)\ - writel(d, (nand_cs_base + OFFS(GPMC_NAND_CMD))) + writel(d, &nand_cs_base->nand_cmd) #define WRITE_NAND_ADDRESS(d, adr)\ - writel(d, (nand_cs_base + OFFS(GPMC_NAND_ADR))) -#define WRITE_NAND(d, adr) writew(d, (nand_cs_base + OFFS(GPMC_NAND_DAT))) -#define READ_NAND(adr) readl((nand_cs_base + OFFS(GPMC_NAND_DAT))) + writel(d, &nand_cs_base->nand_adr) +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
/* Other NAND Access APIs */ -#define NAND_WP_OFF() do {readl(GPMC_CONFIG_REG) |= GPMC_CONFIG_WP; } while (0) -#define NAND_WP_ON() do {readl(GPMC_CONFIG_REG) &= ~GPMC_CONFIG_WP; } while (0) +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ + while (0) +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ + while (0) #define NAND_DISABLE_CE(nand) #define NAND_ENABLE_CE(nand) #define NAND_WAIT_READY(nand) udelay(10) Index: u-boot-arm/include/asm-arm/arch-omap3/omap3.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/omap3.h +++ u-boot-arm/include/asm-arm/arch-omap3/omap3.h @@ -75,7 +75,15 @@
/* 32KTIMER */ #define SYNC_32KTIMER_BASE 0x48320000 -#define S32K_CR 0x10 + +#ifndef __ASSEMBLY__ + +typedef struct s32ktimer { + unsigned char res[0x10]; + unsigned int s32k_cr; /* 0x10 */ +} s32ktimer_t; + +#endif /* __ASSEMBLY__ */
/* OMAP3 GPIO registers */ #define OMAP34XX_GPIO1_BASE 0x48310000 @@ -85,9 +93,15 @@ #define OMAP34XX_GPIO5_BASE 0x49056000 #define OMAP34XX_GPIO6_BASE 0x49058000
-#define GPIO_OE 0x34 -#define GPIO_CLEARDATAOUT 0x90 -#define GPIO_SETDATAOUT 0x94 +#ifndef __ASSEMBLY__ +typedef struct gpio { + unsigned char res1[0x34]; + unsigned int oe; /* 0x34 */ + unsigned char res2[0x58]; + unsigned int cleardataout; /* 0x90 */ + unsigned int setdataout; /* 0x94 */ +} gpio_t; +#endif /* __ASSEMBLY__ */
#define GPIO0 (0x1 << 0) #define GPIO1 (0x1 << 1) Index: u-boot-arm/include/asm-arm/arch-omap3/mem.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/mem.h +++ u-boot-arm/include/asm-arm/arch-omap3/mem.h @@ -25,18 +25,19 @@ #ifndef _MEM_H_ #define _MEM_H_
-#define SDRC_CS0_OSET 0x0 -#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */ +//#define SDRC_CS0_OSET 0x0 +//#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
-#ifndef __ASSEMBLY__ +#define CS0 0x0 +#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
+#ifndef __ASSEMBLY__ typedef enum { STACKED = 0, IP_DDR = 1, COMBO_DDR = 2, IP_SDR = 3, } mem_t; - #endif /* __ASSEMBLY__ */
#define EARLY_INIT 1 Index: u-boot-arm/board/omap3/beagle/beagle.c =================================================================== --- u-boot-arm.orig/board/omap3/beagle/beagle.c +++ u-boot-arm/board/omap3/beagle/beagle.c @@ -62,8 +62,8 @@ int misc_init_r(void) {
unsigned char byte; - unsigned int *gpio5_base = (unsigned int *)OMAP34XX_GPIO5_BASE; - unsigned int *gpio6_base = (unsigned int *)OMAP34XX_GPIO6_BASE; + gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE; + gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
#ifdef CONFIG_DRIVER_OMAP34XX_I2C i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); @@ -97,18 +97,14 @@ int misc_init_r(void) i2c_write(PWRMGT_ADDR_ID3, LEDEN, 1, &byte, 1);
/* Configure GPIOs to output */ - writel(~((GPIO10) | GPIO9 | GPIO3 | GPIO2), - gpio6_base + OFFS(GPIO_OE)); + writel(~((GPIO10) | GPIO9 | GPIO3 | GPIO2), &gpio6_base->oe); writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | - GPIO15 | GPIO14 | GPIO13 | GPIO12), - gpio5_base + OFFS(GPIO_OE)); + GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
/* Set GPIOs */ - writel(GPIO10 | GPIO9 | GPIO3 | GPIO2, - gpio6_base + OFFS(GPIO_SETDATAOUT)); + writel(GPIO10 | GPIO9 | GPIO3 | GPIO2, &gpio6_base->setdataout); writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | - GPIO15 | GPIO14 | GPIO13 | GPIO12, - gpio5_base + OFFS(GPIO_SETDATAOUT)); + GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
return 0; } Index: u-boot-arm/board/omap3/overo/overo.c =================================================================== --- u-boot-arm.orig/board/omap3/overo/overo.c +++ u-boot-arm/board/omap3/overo/overo.c @@ -61,8 +61,8 @@ int misc_init_r(void) {
unsigned char byte; - unsigned int *gpio5_base = (unsigned int *)OMAP34XX_GPIO5_BASE; - unsigned int *gpio6_base = (unsigned int *)OMAP34XX_GPIO6_BASE; + gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE; + gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
#ifdef CONFIG_DRIVER_OMAP34XX_I2C i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); @@ -102,18 +102,14 @@ int misc_init_r(void) i2c_write(PWRMGT_ADDR_ID3, LEDEN, 1, &byte, 1);
/* Configure GPIOs to output */ - writel(~((GPIO10) | GPIO9 | GPIO3 | GPIO2), - gpio6_base + OFFS(GPIO_OE)); + writel(~((GPIO10) | GPIO9 | GPIO3 | GPIO2), &gpio6_base->oe); writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | - GPIO15 | GPIO14 | GPIO13 | GPIO12), - gpio5_base + OFFS(GPIO_OE)); + GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
/* Set GPIOs */ - writel(GPIO10 | GPIO9 | GPIO3 | GPIO2, - gpio6_base + OFFS(GPIO_SETDATAOUT)); + writel(GPIO10 | GPIO9 | GPIO3 | GPIO2, &gpio6_base->setdataout); writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | - GPIO15 | GPIO14 | GPIO13 | GPIO12, - gpio5_base + OFFS(GPIO_SETDATAOUT)); + GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
return 0; } Index: u-boot-arm/board/omap3/pandora/pandora.c =================================================================== --- u-boot-arm.orig/board/omap3/pandora/pandora.c +++ u-boot-arm/board/omap3/pandora/pandora.c @@ -61,10 +61,10 @@ int misc_init_r(void) {
unsigned char byte; - unsigned int *gpio1_base = (unsigned int *)OMAP34XX_GPIO1_BASE; - unsigned int *gpio4_base = (unsigned int *)OMAP34XX_GPIO4_BASE; - unsigned int *gpio5_base = (unsigned int *)OMAP34XX_GPIO5_BASE; - unsigned int *gpio6_base = (unsigned int *)OMAP34XX_GPIO6_BASE; + gpio_t *gpio1_base = (gpio_t *)OMAP34XX_GPIO1_BASE; + gpio_t *gpio4_base = (gpio_t *)OMAP34XX_GPIO4_BASE; + gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE; + gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
#ifdef CONFIG_DRIVER_OMAP34XX_I2C i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); @@ -98,16 +98,15 @@ int misc_init_r(void) i2c_write(PWRMGT_ADDR_ID3, LEDEN, 1, &byte, 1);
/* Configure GPIOs to output */ - writel(~(GPIO14 | GPIO15 | GPIO16 | GPIO23), - gpio1_base + OFFS(GPIO_OE)); - writel(~GPIO22, gpio4_base + OFFS(GPIO_OE)); /* 118 */ + writel(~(GPIO14 | GPIO15 | GPIO16 | GPIO23), &gpio1_base->oe); + writel(~GPIO22, &gpio4_base->oe); /* 118 */ writel(~(GPIO0 | GPIO1 | GPIO28 | GPIO29 | GPIO30 | GPIO31), - gpio5_base + OFFS(GPIO_OE)); /* 128, 129, 156-159 */ - writel(~GPIO4, gpio6_base + OFFS(GPIO_OE)); /* 164 */ + &gpio5_base->oe); /* 128, 129, 156-159 */ + writel(~GPIO4, &gpio6_base->oe); /* 164 */
/* Set GPIOs */ - writel(GPIO28, gpio5_base + OFFS(GPIO_SETDATAOUT)); - writel(GPIO4, gpio6_base + OFFS(GPIO_SETDATAOUT)); + writel(GPIO28, &gpio5_base->setdataout); + writel(GPIO4, &gpio6_base->setdataout);
return 0; } Index: u-boot-arm/cpu/arm_cortexa8/omap3/syslib.c =================================================================== --- u-boot-arm.orig/cpu/arm_cortexa8/omap3/syslib.c +++ u-boot-arm/cpu/arm_cortexa8/omap3/syslib.c @@ -43,26 +43,27 @@ void sdelay(unsigned long loops) /***************************************************************** * sr32 - clear & set a value in a bit range for a 32 bit address *****************************************************************/ -void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value) +void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value) { u32 tmp, msk = 0; msk = 1 << num_bits; --msk; - tmp = readl(addr) & ~(msk << start_bit); + tmp = readl((u32)addr) & ~(msk << start_bit); tmp |= value << start_bit; - writel(tmp, addr); + writel(tmp, (u32)addr); }
/********************************************************************* * wait_on_value() - common routine to allow waiting for changes in * volatile regs. *********************************************************************/ -u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, + u32 bound) { u32 i = 0, val; do { ++i; - val = readl(read_addr) & read_bit_mask; + val = readl((u32)read_addr) & read_bit_mask; if (val == match_value) return 1; if (i == bound) Index: u-boot-arm/include/asm-arm/arch-omap3/sys_proto.h =================================================================== --- u-boot-arm.orig/include/asm-arm/arch-omap3/sys_proto.h +++ u-boot-arm/include/asm-arm/arch-omap3/sys_proto.h @@ -61,8 +61,8 @@ void setup_auxcr(void); void try_unlock_memory(void); u32 get_boot_type(void); void v7_flush_dcache_all(u32); -void sr32(u32, u32, u32, u32); -u32 wait_on_value(u32, u32, u32, u32); +void sr32(void *, u32, u32, u32); +u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); void make_cs1_contiguous(void); void omap_nand_switch_ecc(int);