On Thu, 2018-05-31 at 11:58 +0200, Marek Vasut wrote:
On 05/31/2018 11:50 AM, See, Chin Liang wrote:
On Thu, 2018-05-31 at 11:24 +0200, Marek Vasut wrote:
On 05/31/2018 10:08 AM, tien.fong.chee@intel.com wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
This patchset contains dm driver for DMA330 controller.
This series is working on top of u-boot-socfpga.git - http://git.denx.de/u-boot.git .
Tien Fong Chee (5): drivers: dma: Enable DMA-330 driver support drivers: dma: Add function to zeroes a range of destination such as memory drivers: dma: Factor out dma_get_device from DMA class function include: dma: Update the function description for dma_memcpy arm: dts: socfpga: stratix10: update pdma
arch/arm/dts/socfpga_stratix10.dtsi | 20 + drivers/dma/Kconfig | 9 +- drivers/dma/Makefile | 1 + drivers/dma/dma-uclass.c | 23 +- drivers/dma/dma330.c | 1514 +++++++++++++++++++++++++++++++++++ drivers/mtd/spi/spi_flash.c | 9 +- include/dma.h | 19 +- include/dma330.h | 136 ++++ 8 files changed, 1719 insertions(+), 12 deletions(-) create mode 100644 drivers/dma/dma330.c create mode 100644 include/dma330.h
I presume this is to zero-out the ECC RAM ? Just enable caches and use memset, it is much faster than this DMA witchcraft, at least on the A10.
Yes and no :)
The patch enable DMA-330 support and also zero-out ECC RAM.
Right, that's what I said ?
This driver also enable source to destination transferring through DMA.
While for the speed, DMA still faster as it has larger burst size.
It takes ~0.9s to erase 2 GiB of RAM on the A10. How fast is the DMA?
That is pretty fast. Using DMA dm on Stratix 10 also need around 3-4s for 2GiB DRAM.
Would you mind to share us the codes for enabling the both cache and MMU in SPL. I would like to replicate your changes at Stratix 10 for the performance measurement.
We can also parallel the zero out task with other tasks such as flash controller init.
The flash controller also needs some zeroing out ?
I believe what Chin Liang saying is CPU is free to do other HW initialization while DMA is zeroing the DRAM.
However, current driver is blocking, which means CPU has to wait the DMA finish transferring.
I can pull the DMA transfer status check function out as a new class function so user can check the DMA status at anytime.