- Allow SPL to have .bss disjoint from rest of the image - Allow for .bss setup in CONFIG_SPL_BUILD case too. - Take care of the special case where relocation offset = 0. - Compile out exception handling code and install a simpler vector
Signed-off-by: Aneesh V aneesh@ti.com --- V3: * Taken care of the case where .bss is at a lower address comapred to _start --- arch/arm/cpu/armv7/start.S | 50 ++++++++++++++++++++++++++++++---------- arch/arm/cpu/armv7/u-boot.lds | 2 + 2 files changed, 39 insertions(+), 13 deletions(-)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index d2a6207..5be436f 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -42,7 +42,16 @@ _start: b reset ldr pc, _not_used ldr pc, _irq ldr pc, _fiq - +#ifdef CONFIG_SPL_BUILD +_undefined_instruction: .word _undefined_instruction +_software_interrupt: .word _software_interrupt +_prefetch_abort: .word _prefetch_abort +_data_abort: .word _data_abort +_not_used: .word _not_used +_irq: .word _irq +_fiq: .word _fiq +_pad: .word 0x12345678 /* now 16*4=64 */ +#else _undefined_instruction: .word undefined_instruction _software_interrupt: .word software_interrupt _prefetch_abort: .word prefetch_abort @@ -51,6 +60,8 @@ _not_used: .word not_used _irq: .word irq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ +#endif /* CONFIG_SPL_BUILD */ + .global _end_vect _end_vect:
@@ -89,6 +100,10 @@ _armboot_start: _bss_start_ofs: .word __bss_start - _start
+.global _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: .word __bss_end__ - _start @@ -182,12 +197,11 @@ stack_setup: mov sp, r4
adr r0, _start -#ifndef CONFIG_SPL_BUILD cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ -#endif mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */
copy_loop: @@ -235,20 +249,34 @@ fixnext: add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop + b clear_bss +_rel_dyn_start_ofs: + .word __rel_dyn_start - _start +_rel_dyn_end_ofs: + .word __rel_dyn_end - _start +_dynsym_start_ofs: + .word __dynsym_start - _start + +#endif /* #ifndef CONFIG_SPL_BUILD */
clear_bss: +#ifdef CONFIG_SPL_BUILD + /* No relocation for SPL */ + ldr r0, =__bss_start + ldr r1, =__bss_end__ +#else ldr r0, _bss_start_ofs ldr r1, _bss_end_ofs mov r4, r6 /* reloc addr */ add r0, r0, r4 add r1, r1, r4 +#endif mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 bne clbss_l -#endif /* #ifndef CONFIG_SPL_BUILD */
/* * We are done. Do not return, instead branch to second part of board @@ -276,13 +304,6 @@ jump_2_ram: _board_init_r_ofs: .word board_init_r - _start
-_rel_dyn_start_ofs: - .word __rel_dyn_start - _start -_rel_dyn_end_ofs: - .word __rel_dyn_end - _start -_dynsym_start_ofs: - .word __dynsym_start - _start - /************************************************************************* * * CPU_init_critical registers @@ -327,6 +348,8 @@ cpu_init_crit: bl lowlevel_init @ go setup pll,mux,memory mov lr, ip @ restore link mov pc, lr @ back to my caller + +#ifndef CONFIG_SPL_BUILD /* ************************************************************************* * @@ -514,4 +537,5 @@ fiq: bad_save_user_regs bl do_fiq
-#endif +#endif /* CONFIG_USE_IRQ */ +#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds index dbae54d..40ecf78 100644 --- a/arch/arm/cpu/armv7/u-boot.lds +++ b/arch/arm/cpu/armv7/u-boot.lds @@ -55,6 +55,8 @@ SECTIONS
. = ALIGN(4);
+ __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*)