4 Mar
2014
4 Mar
'14
8:14 p.m.
On Tue, Feb 18, 2014 at 07:31:57AM -0500, Tom Rini wrote:
From: Lokesh Vutla lokeshvutla@ti.com
Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD registers. In EMIF_PHY_CTRL: Updating [4:0]READ_LATENCY to 8, because at higher frequencies like 400MHz the read latency expected will be CL+3 as per tests from HW folks. Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug purpose. With out this resume is not working(Still waiting for PHY team to come back for better explanation).
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Applied to u-boot-ti/master, thanks!
--
Tom