[PATCH 2/2] riscv: jh7110: enable riscv,timer in the device tree

The JH7110 has the arhitectural CPU timer on all 5 rv64 cores. Note that in the device tree.

Signed-off-by: Torsten Duwe duwe@suse.de --- arch/riscv/dts/jh7110.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 081b833331..ec237a46ff 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -163,6 +163,15 @@ }; };

+ timer { + compatible = "riscv,timer"; + interrupts-extended = <&cpu0_intc 5>, + <&cpu1_intc 5>, + <&cpu2_intc 5>, + <&cpu3_intc 5>, + <&cpu4_intc 5>; + }; + osc: oscillator { compatible = "fixed-clock"; clock-output-names = "osc";