From: Nagabhushana Netagunte nagabhushana.netagunte@ti.com
Add support for DSP wake-up by default on DA850/OMAP-L138 during board initialization. To prevent DSP from being woken up, set the environment variable dspwake to 'no'.
Signed-off-by: Sekhar Nori nsekhar@ti.com Signed-off-by: Nagabhushana Netagunte nagabhushana.netagunte@ti.com --- arch/arm/include/asm/arch-davinci/hardware.h | 5 +++ board/davinci/da8xxevm/da850evm.c | 51 ++++++++++++++++++++++++++ 2 files changed, 56 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index d2b2989..c41d756 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -151,7 +151,12 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000 #define DAVINCI_INTC_BASE 0xfffee000 #define DAVINCI_BOOTCFG_BASE 0x01c14000 +#define DAVINCI_L3CBARAM_BASE 0x80000000 #define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18) +#define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24) +#define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44) +#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00) +
#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38) #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 8d09bb9..f7754fe 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -424,6 +424,55 @@ err_probe: return ret; }
+void dsp_lpsc_on(unsigned domain, unsigned int id) +{ + dv_reg_p mdstat, mdctl, ptstat, ptcmd; + struct davinci_psc_regs *psc_regs; + + psc_regs = davinci_psc0_regs; + mdstat = &psc_regs->psc0.mdstat[id]; + mdctl = &psc_regs->psc0.mdctl[id]; + ptstat = &psc_regs->ptstat; + ptcmd = &psc_regs->ptcmd; + + while (*ptstat & (0x1 << domain)) + ; + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + *ptcmd = 0x1 << domain; + + while (*ptstat & (0x1 << domain)) + ; + while ((*mdstat & 0x1f) != 0x03) + ; /* Probably an overkill... */ +} + +static void dspwake(void) +{ + unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; + + /* if the device is ARM only, return */ + if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10) + return; + + if (!strcmp(getenv("dspwake"), "no")) + return; + + *resetvect++ = 0x1E000; /* DSP Idle */ + /* clear out the next 10 words as NOP */ + memset(resetvect, 0, sizeof(unsigned) * 10); + + /* setup the DSP reset vector */ + REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE; + + dsp_lpsc_on(1, DAVINCI_LPSC_GEM); + REG(PSC0_MDCTL + (15 * 4)) |= 0x100; +} + int misc_init_r(void) { uint8_t tmp[20], addr[10]; @@ -447,5 +496,7 @@ int misc_init_r(void) setenv("ethaddr", (char *)tmp); }
+ dspwake(); + return 0; }