28 Feb
2019
28 Feb
'19
7:56 p.m.
On Thu, 28 Feb 2019 22:45 Baruch Siach, baruch@tkos.co.il wrote:
Hi Chris,
Currently the value of g_odt_config is hard coded in Marvell SoC platform headers. Some SolidRun A388 SOMs need a custom value. These SOMs use both DDR chip-selects, but ODT0 alone is connected to both chips. For that to work we need to set g_odt_config to 0x30000, that is, ODT0 is configured for both CS0 and CS1.
How can we do that in a clean way so as to not interfere too much with your periodic code syncs from Marvell's DDR training source tree?
I've actually got a patch from marvell that might help. I'll send it to the list when I'm at a proper keyboard.