Re: [U-Boot-Users] Accessing IRAM & DRAM through different segments in MIPS

Viswanath Bandi wrote:

Thanks Shinya & Donald for the suggestions.

Following is our cache configuration.

Cache Size (KB): 8KBytes Associativity (Lines Per Set): 4-Ways Way Size (KB): 2KBytes Number of Sets:128 Sets Cache Line Size: 16-bytes per line

One more thing I found out is that the cache works when configured in write-through mode (with or without write allocate). The only mode which is giving problem is "write-back, write allocate".

Ok. I'd like to make sure that

* Which version of U-Boot do you use?

* How do you configure CFGs below? - CFG_ICACHE_SIZE - CFG_DCACHE_SIZE - CFG_CACHELINE_SIZE

And if possible, please post the diff regarding `cpu/mips' like this,

$ diff -uprN u-boot-X.Y.Z{.orig,-yours}/cpu/mips > my.patch

Thanks in advance,

Shinya