Change-Id: Ib823620ff7940f8d62e78010817ca9b5f06995dd Signed-off-by: Elaine Zhang zhangqing@rock-chips.com --- drivers/clk/rockchip/clk_rk3568.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 469014439be4..7b9035acdb0f 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -1839,7 +1839,7 @@ static ulong rk3568_dclk_vop_set_clk(struct rk3568_clk_priv *priv, rockchip_pll_set_rate(&rk3568_pll_clks[VPLL], priv->cru, VPLL, div * rate); } else { - for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) { + for (i = sel; i <= DCLK_VOP_SEL_CPLL; i++) { switch (i) { case DCLK_VOP_SEL_GPLL: pll_rate = priv->gpll_hz; @@ -2964,9 +2964,15 @@ static int rk3568_dclk_vop_set_parent(struct clk *clk, struct clk *parent) if (parent->id == PLL_VPLL) { rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK, DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT); - } else { + } else if (parent->id == PLL_HPLL) { rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK, DCLK_VOP_SEL_HPLL << DCLK0_VOP_SEL_SHIFT); + } else if (parent->id == PLL_CPLL) { + rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK, + DCLK_VOP_SEL_CPLL << DCLK0_VOP_SEL_SHIFT); + } else { + rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK, + DCLK_VOP_SEL_GPLL << DCLK0_VOP_SEL_SHIFT); }
return 0;