The physical base address of the NOR flash is 0x1e000000 on the Malta boards. The hardware also maps the first 4MiB of the flash into the 0x1fc00000-0x1fffffff range.
Currently, U-Boot uses the mapped address to access the flash, which does not work in recent qemu versions.
Since commit a427338b222b43197c2776cbc996936df0302f51 (mips_malta: correct reading MIPS revision at 0x1fc00010) writing to the mapped address space causes a CPU exception. Due to the exception, U-Boot hangs during boot when it tries to detect the CFI flash chip.
Use the correct physical address for the MALTA_FLASH_BASE constant to fix the problem. In order to avoid relocation problems, also update the CONFIG_SYS_{TEXT,MONITOR}_BASE constants.
The change makes it possible to start U-Boot on a Malta board emulated with Qemu 1.6.1 and 1.7.0-rc0. It also works on older versions (tested with 1.1.1, 1.2.2, 1.4.2, 1.5.3).
Signed-off-by: Gabor Juhos juhosg@openwrt.org Signed-off-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Paul Burton paul.burton@imgtec.com --- Changes since v1: - update CONFIG_SYS_{TEXT,MONITOR}_BASE constants - update commit message --- arch/mips/include/asm/malta.h | 2 +- include/configs/malta.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index 9b1100b..bd9043d 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -44,7 +44,7 @@ #define MALTA_RESET_BASE 0x1f000500 #define GORESET 0x42
-#define MALTA_FLASH_BASE 0x1fc00000 +#define MALTA_FLASH_BASE 0x1e000000
#define MALTA_REVISION 0x1fc00010 #define MALTA_REVISION_CORID_SHF 10 diff --git a/include/configs/malta.h b/include/configs/malta.h index 4098e72..458c33a 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -40,8 +40,8 @@ /* * Memory map */ -#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_TEXT_BASE 0xbe000000 /* Rom version */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ #define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024)