Re: [PATCH] arm64: zynqmp: Fix issue of apps executing from R5 core 1

On 4/5/23 15:06, Michal Simek wrote:

From: Ashok Reddy Soma ashok.reddy.soma@amd.com

In current implementation, applications can execute only on R5 core 0. The boot address for R5 core 1 is not supplied. Pass TCM address for R5 core 1 based on the argument to fix the issue.

Remove incomplete comment.

Signed-off-by: Ashok Reddy Soma ashok.reddy.soma@amd.com Signed-off-by: Michal Simek michal.simek@amd.com

---

arch/arm/mach-zynqmp/mp.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index d98c34ea8a5a..7a12f4b2b6c7 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -32,7 +32,8 @@ #define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK 0x02 #define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000

-#define ZYNQMP_TCM_START_ADDRESS 0xFFE00000 +#define ZYNQMP_R5_0_TCM_START_ADDR 0xFFE00000 +#define ZYNQMP_R5_1_TCM_START_ADDR 0xFFE90000 #define ZYNQMP_TCM_BOTH_SIZE 0x40000

#define ZYNQMP_CORE_APU0 0 @@ -215,9 +216,14 @@ static void set_r5_start(u8 high) writel(tmp, &rpu_base->rpu1_cfg); }

-static void write_tcm_boot_trampoline(u32 boot_addr) +static void write_tcm_boot_trampoline(u32 nr, u32 boot_addr) { if (boot_addr) {

• u64 tcm_start_addr = ZYNQMP_R5_0_TCM_START_ADDR;
  

• if (nr == ZYNQMP_CORE_RPU1)
  

• 	tcm_start_addr = ZYNQMP_R5_1_TCM_START_ADDR;
  

• /*
  • Boot trampoline is simple ASM code below.

@@ -229,12 +235,12 @@ static void write_tcm_boot_trampoline(u32 boot_addr) * bx r1 */ debug("Write boot trampoline for %x\n", boot_addr);

• writel(0xea000000, ZYNQMP_TCM_START_ADDRESS);
  

• writel(boot_addr, ZYNQMP_TCM_START_ADDRESS + 0x4);
  

• writel(0xe59f0004, ZYNQMP_TCM_START_ADDRESS + 0x8);
  

• writel(0xe5901000, ZYNQMP_TCM_START_ADDRESS + 0xc);
  

• writel(0xe12fff11, ZYNQMP_TCM_START_ADDRESS + 0x10);
  

• writel(0x00000004, ZYNQMP_TCM_START_ADDRESS + 0x14); // address for
  

• writel(0xea000000, tcm_start_addr);
  

• writel(boot_addr, tcm_start_addr + 0x4);
  

• writel(0xe59f0004, tcm_start_addr + 0x8);
  

• writel(0xe5901000, tcm_start_addr + 0xc);
  

• writel(0xe12fff11, tcm_start_addr + 0x10);
  

• writel(0x00000004, tcm_start_addr + 0x14);
  

  } }

@@ -328,7 +334,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) enable_clock_r5(); release_r5_reset(nr, LOCK); dcache_disable();

• 	write_tcm_boot_trampoline(boot_addr_uniq);
  

• 	write_tcm_boot_trampoline(nr, boot_addr_uniq);
  dcache_enable();
  set_r5_halt_mode(nr, RELEASE, LOCK);
  mark_r5_used(nr, LOCK);
  

@@ -341,7 +347,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) enable_clock_r5(); release_r5_reset(nr, SPLIT); dcache_disable();

• 	write_tcm_boot_trampoline(boot_addr_uniq);
  

• 	write_tcm_boot_trampoline(nr, boot_addr_uniq);
  dcache_enable();
  set_r5_halt_mode(nr, RELEASE, SPLIT);
  mark_r5_used(nr, SPLIT);
  

Applied. M