Hi Svyatoslav,
On Mon, 24 Oct 2022 at 00:26, Svyatoslav Ryhel clamor95@gmail.com wrote:
Add timer support for T20/T30/T114 and T124 based devices. Driver is based on DM, has device tree support and can be used on SPL and early boot stage.
Tested-by: Andreas Westman Dorcsak hedmoo@yahoo.com # ASUS TF600T T30 Tested-by: Jonas Schwöbel jonasschwoebel@yahoo.de # Surface RT T30 Tested-by: Robert Eckelmann longnoserob@gmail.com # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel clamor95@gmail.com # LG P895 T30 Co-developed-by: Jonas Schwöbel jonasschwoebel@yahoo.de Signed-off-by: Jonas Schwöbel jonasschwoebel@yahoo.de Signed-off-by: Svyatoslav Ryhel clamor95@gmail.com
drivers/timer/Kconfig | 8 +++ drivers/timer/Makefile | 1 + drivers/timer/tegra-timer.c | 124 ++++++++++++++++++++++++++++++++++++ 3 files changed, 133 insertions(+) create mode 100644 drivers/timer/tegra-timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index fd8745ffc2..702ffd3084 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -244,6 +244,14 @@ config STM32_TIMER Select this to enable support for the timer found on STM32 devices.
+config TEGRA_TIMER
bool "Tegra timer support"depends on TIMERselect TIMER_EARLYhelpSelect this to enable support for the timer found onTegra devices.config X86_TSC_TIMER bool "x86 Time-Stamp Counter (TSC) timer support" depends on TIMER && X86 diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 7bfb7749e9..ccbff05d43 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o obj-$(CONFIG_STI_TIMER) += sti-timer.o obj-$(CONFIG_STM32_TIMER) += stm32_timer.o +obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c new file mode 100644 index 0000000000..cda460921f --- /dev/null +++ b/drivers/timer/tegra-timer.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2022 Svyatoslav Ryhel clamor95@gmail.com
- */
+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <timer.h>
+#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/tegra.h>
+#define TEGRA_OSC_CLK_ENB_L_SET (NV_PA_CLK_RST_BASE + 0x320) +#define TEGRA_OSC_SET_CLK_ENB_TMR BIT(5)
+#define TEGRA_TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) +#define TEGRA_TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4)
+#define TEGRA_TIMER_RATE 1000000 /* 1 MHz */
+u64 notrace timer_early_get_count(void) +{
/* At this stage raw timer is used */return readl(TEGRA_TIMER_USEC_CNTR);+}
+unsigned long notrace timer_early_get_rate(void) +{
return TEGRA_TIMER_RATE;+}
+#if CONFIG_IS_ENABLED(BOOTSTAGE) +ulong timer_get_boot_us(void) +{
u64 ticks = 0;int ret;ret = dm_timer_init();
You cannot necessarily call this here...does it work when bootstage is enabled?
Regards, Simon