Dear Wolfgang,
Which part of section "Initial Stack, Global Data" in the README don't you understand?
Thanks for pointing out the section. I didn't read it through before. :(
stack in DCACHE (Walnut 405 is an example). But the CFG_INIT_RAM_ADDR is 0x40000000, which is inside SDRAM. Why was it commented that the
No, this is not inside SDRAM. There is no board (yet) with 1 GB of RAM.
Well, "inside SDRAM" is what is commented on WALNUT.h. Now I understand the value of CFG_INIT_RAM_ADDR is better not to interfere with the system design.
In short: cache is like normal memory, just very fast (which does not play a role here). We just have to make sure that no cache fills or cache flushes will be done (at least not for that part of the data cache which is being used for the initial stack).
I don't see any caches are in a system memory mapping. Then I thought it could be only accessed by those cache specific instructions, like dcread. That's my misunderstanding.
Thanks, -Shawn.