Mans Rullgard wrote:
This is required to work around ARM erratum 621766, affecting Cortex-A8 r1p0-3:
When a sequence of Neon load instructions is intermixed with several branches, some of which are mispredicted, it is possible for the processor to deadlock due to Neon loads on the speculative path not being properly flushed from the Neon load queue.
Signed-off-by: Mans Rullgard mans@mansr.com
Acked-by: Dirk Behme dirk.behme@gmail.com
---
Jean-Christophe: This is for u-boot-arm/omap3, so please read the subject as "[PATCH-OMAP3] OMAP3: ..."
cpu/arm_cortexa8/omap3/board.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 90809a6..7c2a7ea 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -139,6 +139,8 @@ void setup_auxcr() __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); /* Enabling ASA */ __asm__ __volatile__("orr r0, r0, #0x10");
- /* Enable L1NEON */
- __asm__ __volatile__("orr r0, r0, #1<<5"); /* SMI instruction to call ROM Code API */ __asm__ __volatile__(".word 0xE1600070"); __asm__ __volatile__("mov r0, %0":"=r"(i));