Re: [U-Boot] [PATCH 5/8] sunxi: Add selective DRAM type and timing

On 11/03/17 16:19, Icenowy Zheng wrote:

DRAM chip varies, and one code cannot satisfy all DRAMs.

Add options to select a timing set.

Currently only DDR3-1333 (the original set) is added into it.

Yes, separating the timings sounds like a good idea. Eventually we should move these parameters into a data structure, but let's start easy here and do one step after another (unless you feel bored and want to mimic how Philipp did it [1]).

Signed-off-by: Icenowy Zheng icenowy@aosc.xyz

Reviewed-by: Andre Przywara andre.przywara@arm.com

Icenowy, if you rebase this, take care to not loose the H5 changes from the sunxi/master branch (make sure that ddr3_1333.c contains a copy of the latest code, not just from this version of the patch here).

Cheers, Andre.

[1] https://github.com/ptomsich/u-boot/commit/4ae474c756c3208a3bfaf36ed6f1850d46...

---

arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h | 30 ++++++ arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/dram_sunxi_dw.c | 116 ++---------------------- arch/arm/mach-sunxi/dram_timings/Makefile | 1 + arch/arm/mach-sunxi/dram_timings/ddr3_1333.c | 84 +++++++++++++++++ board/sunxi/Kconfig | 18 ++++ 6 files changed, 140 insertions(+), 110 deletions(-) create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c

diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h index 48bd6f7c0f..61da150c14 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h @@ -191,4 +191,34 @@ struct sunxi_mctl_ctl_reg { #define DXBDLR_WRITE_DELAY(x) ((x) << 8) #define DXBDLR_READ_DELAY(x) ((x) << 0)

+/*

• • The delay parameters below allow to allegedly specify delay times of some
• • unknown unit for each individual bit trace in each of the four data bytes
• • the 32-bit wide access consists of. Also three control signals can be
• • adjusted individually.
• */

+#define BITS_PER_BYTE 8 +#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) +/* The eight data lines (DQn) plus DM, DQS and DQSN */ +#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) +struct dram_para {

• u16 page_size;
• u8 bus_full_width;
• u8 dual_rank;
• u8 row_bits;
• u8 bank_bits;
• const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
• const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
• const u8 ac_delays[31];

+};

+static inline int ns_to_t(int nanoseconds) +{

• const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
• return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);

+}

+void mctl_set_timing_params(uint16_t socid, struct dram_para *para);

#endif /* _SUNXI_DRAM_SUN8I_H3_H */ diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index b8f01e3b61..e1b6fe8d5c 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o obj-$(CONFIG_SUNXI_DRAM_DW) += dram_sunxi_dw.o +obj-$(CONFIG_SUNXI_DRAM_DW) += dram_timings/ obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o obj-$(CONFIG_MACH_SUN50I) += dram_sun8i_h3.o endif diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index bb4457d2b8..401f6a4624 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -16,34 +16,6 @@ #include <asm/arch/cpu.h> #include <linux/kconfig.h>

-/*

• • The delay parameters below allow to allegedly specify delay times of some
• • unknown unit for each individual bit trace in each of the four data bytes
• • the 32-bit wide access consists of. Also three control signals can be
• • adjusted individually.
• */

-#define BITS_PER_BYTE 8 -#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) -/* The eight data lines (DQn) plus DM, DQS and DQSN */ -#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) -struct dram_para {

• u16 page_size;
• u8 bus_full_width;
• u8 dual_rank;
• u8 row_bits;
• u8 bank_bits;
• const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
• const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
• const u8 ac_delays[31];

-};

-static inline int ns_to_t(int nanoseconds) -{

• const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
• return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);

-}

static void mctl_phy_init(u32 val) { struct sunxi_mctl_ctl_reg * const mctl_ctl = @@ -190,87 +162,6 @@ static void mctl_set_master_priority(uint16_t socid) } }

-static void mctl_set_timing_params(uint16_t socid, struct dram_para *para) -{

• struct sunxi_mctl_ctl_reg * const mctl_ctl =

• 	(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  

• u8 tccd = 2;
• u8 tfaw = ns_to_t(50);
• u8 trrd = max(ns_to_t(10), 4);
• u8 trcd = ns_to_t(15);
• u8 trc = ns_to_t(53);
• u8 txp = max(ns_to_t(8), 3);
• u8 twtr = max(ns_to_t(8), 4);
• u8 trtp = max(ns_to_t(8), 4);
• u8 twr = max(ns_to_t(15), 3);
• u8 trp = ns_to_t(15);
• u8 tras = ns_to_t(38);
• u16 trefi = ns_to_t(7800) / 32;
• u16 trfc = ns_to_t(350);
• u8 tmrw = 0;
• u8 tmrd = 4;
• u8 tmod = 12;
• u8 tcke = 3;
• u8 tcksrx = 5;
• u8 tcksre = 5;
• u8 tckesr = 4;
• u8 trasmax = 24;
• u8 tcl = 6; /* CL 12 */
• u8 tcwl = 4; /* CWL 8 */
• u8 t_rdata_en = 4;
• u8 wr_latency = 2;
• u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
• u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
• u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
• u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
• u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
• u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
• u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
• /* set mode register */
• writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
• writel(0x40, &mctl_ctl->mr[1]);
• writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
• writel(0x0, &mctl_ctl->mr[3]);
• /* set DRAM timing */
• writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |

•       DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
  

•       &mctl_ctl->dramtmg[0]);
  

• writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),

•       &mctl_ctl->dramtmg[1]);
  

• writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |

•       DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
  

•       &mctl_ctl->dramtmg[2]);
  

• writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),

•       &mctl_ctl->dramtmg[3]);
  

• writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |

•       DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
  

• writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |

•       DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
  

•       &mctl_ctl->dramtmg[5]);
  

• /* set two rank timing */
• clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),

• 	(0x66 << 8) | (0x10 << 0));
  

• /* set PHY interface timing, write latency and read latency configure */
• writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |

•       (wr_latency << 0), &mctl_ctl->pitmg[0]);
  

• /* set PHY timing, PTR0-2 use default */
• writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
• writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
• /* set refresh timing */
• writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);

-}

static u32 bin_to_mgray(int val) { static const u8 lookup_table[32] = { @@ -367,7 +258,12 @@ static void mctl_set_cr(struct dram_para *para) struct sunxi_mctl_com_reg * const mctl_com = (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;

• writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |

• writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_INTERLEAVED |

+#if defined CONFIG_SUNXI_DRAM_DDR3

•       MCTL_CR_DDR3 |
  

+#else +#error Unsupported DRAM type! +#endif (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) | MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) | (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile new file mode 100644 index 0000000000..7e71c76a5c --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o diff --git a/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c new file mode 100644 index 0000000000..8e082c735a --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/ddr3_1333.c @@ -0,0 +1,84 @@ +#include <common.h> +#include <asm/arch/dram.h> +#include <asm/arch/cpu.h>

+void mctl_set_timing_params(uint16_t socid, struct dram_para *para) +{

• struct sunxi_mctl_ctl_reg * const mctl_ctl =

• 	(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  

• u8 tccd = 2;
• u8 tfaw = ns_to_t(50);
• u8 trrd = max(ns_to_t(10), 4);
• u8 trcd = ns_to_t(15);
• u8 trc = ns_to_t(53);
• u8 txp = max(ns_to_t(8), 3);
• u8 twtr = max(ns_to_t(8), 4);
• u8 trtp = max(ns_to_t(8), 4);
• u8 twr = max(ns_to_t(15), 3);
• u8 trp = ns_to_t(15);
• u8 tras = ns_to_t(38);
• u16 trefi = ns_to_t(7800) / 32;
• u16 trfc = ns_to_t(350);
• u8 tmrw = 0;
• u8 tmrd = 4;
• u8 tmod = 12;
• u8 tcke = 3;
• u8 tcksrx = 5;
• u8 tcksre = 5;
• u8 tckesr = 4;
• u8 trasmax = 24;
• u8 tcl = 6; /* CL 12 */
• u8 tcwl = 4; /* CWL 8 */
• u8 t_rdata_en = 4;
• u8 wr_latency = 2;
• u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
• u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
• u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
• u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
• u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
• u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
• u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
• /* set mode register */
• writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
• writel(0x40, &mctl_ctl->mr[1]);
• writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
• writel(0x0, &mctl_ctl->mr[3]);
• /* set DRAM timing */
• writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |

•       DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
  

•       &mctl_ctl->dramtmg[0]);
  

• writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),

•       &mctl_ctl->dramtmg[1]);
  

• writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |

•       DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
  

•       &mctl_ctl->dramtmg[2]);
  

• writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),

•       &mctl_ctl->dramtmg[3]);
  

• writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |

•       DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
  

• writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |

•       DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
  

•       &mctl_ctl->dramtmg[5]);
  

• /* set two rank timing */
• clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),

• 	(0x66 << 8) | (0x10 << 0));
  

• /* set PHY interface timing, write latency and read latency configure */
• writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |

•       (wr_latency << 0), &mctl_ctl->pitmg[0]);
  

• /* set PHY timing, PTR0-2 use default */
• writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
• writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
• /* set refresh timing */
• writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);

+} diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index d8a1e341e8..7e03ee8b36 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -192,6 +192,24 @@ config ARM_BOOT_HOOK_RMR This allows both the SPL and the U-Boot proper to be entered in either mode and switch to AArch64 if needed.

+if SUNXI_DRAM_DW +config SUNXI_DRAM_DDR3

• bool

+choice

• prompt "DRAM Type and Timing"
• default SUNXI_DRAM_DDR3_1333

+config SUNXI_DRAM_DDR3_1333

• bool "DDR3 1333"
• select SUNXI_DRAM_DDR3
• ---help---
• This option is the original only supported memory type, which suits
• many H3/H5/A64 boards available now.

+endchoice +endif

config DRAM_TYPE int "sunxi dram type" depends on MACH_SUN8I_A83T