From: Shinya Kuribayashi skuribay@ruby.dti.ne.jp
No logical changes.
Signed-off-by: Shinya Kuribayashi skuribay@ruby.dti.ne.jp ---
cpu/mips/cache.S | 30 +++++++++++++----------------- cpu/mips/cpu.c | 6 +++--- cpu/mips/start.S | 50 +++++++++++++++++++++++--------------------------- 3 files changed, 39 insertions(+), 47 deletions(-)
diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index aad76e0..443240e 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -22,7 +22,6 @@ * MA 02111-1307 USA */
- #include <config.h> #include <version.h> #include <asm/regdef.h> @@ -30,13 +29,11 @@ #include <asm/addrspace.h> #include <asm/cacheops.h>
- /* 16KB is the maximum size of instruction and data caches on * MIPS 4K. */ #define MIPS_MAX_CACHE_SIZE 0x4000
- /* * cacheop macro to automate cache operations * first some helpers... @@ -131,7 +128,6 @@ mips_cache_reset: li t4, CFG_CACHELINE_SIZE move t5, t4
- li v0, MIPS_MAX_CACHE_SIZE
/* Now clear that much memory starting from zero. @@ -139,8 +135,8 @@ mips_cache_reset:
li a0, KSEG1 addu a1, a0, v0 - -2: sw zero, 0(a0) +2: + sw zero, 0(a0) sw zero, 4(a0) sw zero, 8(a0) sw zero, 12(a0) @@ -156,11 +152,11 @@ mips_cache_reset:
mtc0 zero, CP0_TAGLO
- /* - * The caches are probably in an indeterminate state, - * so we force good parity into them by doing an - * invalidate, load/fill, invalidate for each line. - */ + /* + * The caches are probably in an indeterminate state, + * so we force good parity into them by doing an + * invalidate, load/fill, invalidate for each line. + */
/* Assume bottom of RAM will generate good parity for the cache. */ @@ -201,9 +197,9 @@ mips_cache_reset: move a1, a2 icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
- j ra - .end mips_cache_reset + j ra
+ .end mips_cache_reset
/******************************************************************************* * @@ -220,7 +216,7 @@ dcache_status: andi v0, v0, 1 j ra
- .end dcache_status + .end dcache_status
/******************************************************************************* * @@ -237,11 +233,10 @@ dcache_disable: li t1, -8 and t0, t0, t1 ori t0, t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG + mtc0 t0, CP0_CONFIG j ra
- .end dcache_disable - + .end dcache_disable
/******************************************************************************* * @@ -266,4 +261,5 @@ mips_cache_lock: icacheop(a0,a1,a2,a3,0x1d)
j ra + .end mips_cache_lock diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index f48675e..7559ac6 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -39,12 +39,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; }
-void flush_cache (ulong start_addr, ulong size) +void flush_cache(ulong start_addr, ulong size) { - }
-void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){ +void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) +{ write_32bit_cp0_register(CP0_ENTRYLO0, low0); write_32bit_cp0_register(CP0_PAGEMASK, pagemask); write_32bit_cp0_register(CP0_ENTRYLO1, low1); diff --git a/cpu/mips/start.S b/cpu/mips/start.S index 074d01d..5a278b6 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -22,13 +22,11 @@ * MA 02111-1307 USA */
- #include <config.h> #include <version.h> #include <asm/regdef.h> #include <asm/mipsregs.h>
- #define RVECENT(f,n) \ b f; nop #define XVECENT(f,bev) \ @@ -192,7 +190,7 @@ _start: .word 0x00000000 .word 0x03e00008 .word 0x00000000 - .word 0x00000000 + .word 0x00000000 /* 0xbfc00428 */ .word 0xdc870000 .word 0xfca70000 @@ -203,7 +201,7 @@ _start: .word 0x00000000 .word 0x03e00008 .word 0x00000000 - .word 0x00000000 + .word 0x00000000 #endif /* CONFIG_PURPLE */ .align 4 reset: @@ -235,33 +233,33 @@ reset: mtc0 t0, CP0_CONFIG
/* Initialize $gp. - */ - bal 1f + */ + bal 1f nop .word _gp - 1: - move gp, ra - lw t1, 0(ra) +1: + move gp, ra + lw t1, 0(ra) move gp, t1
#ifdef CONFIG_INCA_IP /* Disable INCA-IP Watchdog. */ - la t9, disable_incaip_wdt - jalr t9 + la t9, disable_incaip_wdt + jalr t9 nop #endif
/* Initialize any external memory. */ - la t9, lowlevel_init - jalr t9 + la t9, lowlevel_init + jalr t9 nop
/* Initialize caches... */ - la t9, mips_cache_reset - jalr t9 + la t9, mips_cache_reset + jalr t9 nop
/* ... and enable them. @@ -269,12 +267,11 @@ reset: li t0, CONF_CM_CACHABLE_NONCOHERENT mtc0 t0, CP0_CONFIG
- /* Set up temporary stack. */ li a0, CFG_INIT_SP_OFFSET - la t9, mips_cache_lock - jalr t9 + la t9, mips_cache_lock + jalr t9 nop
li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET @@ -284,7 +281,6 @@ reset: j t9 nop
- /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -298,7 +294,7 @@ reset: .globl relocate_code .ent relocate_code relocate_code: - move sp, a0 /* Set new stack pointer */ + move sp, a0 /* Set new stack pointer */
li t0, CFG_MONITOR_BASE la t3, in_ram @@ -312,8 +308,8 @@ relocate_code: */ move t6, gp sub gp, CFG_MONITOR_BASE - add gp, a2 /* gp now adjusted */ - sub t6, gp, t6 /* t6 <-- relocation offset */ + add gp, a2 /* gp now adjusted */ + sub t6, gp, t6 /* t6 <-- relocation offset */
/* * t0 = source address @@ -329,7 +325,7 @@ relocate_code: sw t3, 0(t1) addu t0, 4 ble t0, t2, 1b - addu t1, 4 /* delay slot */ + addu t1, 4 /* delay slot */ #endif
/* If caches were enabled, we would have to flush them here. @@ -376,7 +372,8 @@ in_ram: add t2, t6
sub t1, 4 -1: addi t1, 4 +1: + addi t1, 4 bltl t1, t2, 1b sw zero, 0(t1) /* delay slot */
@@ -387,11 +384,10 @@ in_ram:
.end relocate_code
- /* Exception handlers. */ romReserved: - b romReserved + b romReserved
romExcHandle: - b romExcHandle + b romExcHandle