26 Jul
2010
26 Jul
'10
8:15 p.m.
On Jul 14, 2010, at 10:14 AM, Kumar Gala wrote:
From: york yorksun@freescale.com
Previous code presumes each DIMM has up to two rank (chip select). Newer DDR controller supports up to four chip select on one DIMM.
Signed-off-by: York Sun yorksun@freescale.com
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 52 ++++++++++++++----- .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c | 12 +++++ arch/powerpc/cpu/mpc8xxx/ddr/options.c | 17 ++++--- arch/powerpc/include/asm/fsl_ddr_sdram.h | 1 + 4 files changed, 61 insertions(+), 21 deletions(-)
applied to 85xx
- k