Current SPL code base has BSS section placed after reset_vector. This means they have to relocate to use the global variables. This put an implicit requirement of having SPL size = Memory/2.
To avoid relocation, move bss_section within SPL range.
Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com --- arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index bc13267..ffc6ad3 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -57,13 +57,34 @@ SECTIONS . = ALIGN(8); __init_begin = .; __init_end = .; +#ifdef CONFIG_SKIP_RELOCATE_SPL + /* + * Make sure that the bss segment isn't linked at 0x0, otherwise its + * address won't be updated during relocation fixups. + */ + . |= 0x10; + + . = ALIGN(4); + __bss_start = .; + .bss : { + *(.sbss*) + *(.bss*) + } + . = ALIGN(4); + __bss_end = .; +#endif /* FIXME for non-NAND SPL */ #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ - .bootpg ADDR(.text) + 0x1000 : +#ifndef BOOT_PAGE_OFFSET +#define BOOT_PAGE_OFFSET 0x1000 +#endif + .bootpg ADDR(.text) + BOOT_PAGE_OFFSET : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) } +#ifndef RESET_VECTOR_OFFSET #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ +#endif #elif defined(CONFIG_FSL_ELBC) #define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ #else @@ -80,6 +101,7 @@ SECTIONS } = 0xffff #endif
+#ifndef CONFIG_SKIP_RELOCATE_SPL /* * Make sure that the bss segment isn't linked at 0x0, otherwise its * address won't be updated during relocation fixups. @@ -94,4 +116,5 @@ SECTIONS } . = ALIGN(4); __bss_end = .; +#endif }