On Tuesday 02 December 2008, Dave Liu wrote:
we load the secondary stage u-boot image from NAND to system memory by nand_load, but we did not flush d-cache to memory, not invalidate i-cache before we jump to RAM. when the system is cache enable and the TLB/page attribute of system memory is cacheable, it will cause issue.
- 83xx family is using the d-cache lock, so all of d-cache access is cache-inhibited. so you can't see the issue.
- 85xx family is using d-cache, i-cache enable, partial cache lock. you will see the issue.
The patch fix the cache issue.
Signed-off-by: Dave Liu daveliu@freescale.com
Stefan,
I'm not familiar with ppc4xx, could you workout one patch for nand_boot.c?
All 4xx platforms using nand_boot.c run with D-Cache disabled at that time. So it's currently not needed here.
Best regards, Stefan
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