From: Michael Trimarchi michael@amarulasolutions.com
This commit ensures that critical clock paths are not disabled during reparent and set_rate operations within the clock framework, paving the way for the inclusion of new features.
Signed-off-by: Michael Trimarchi michael@amarulasolutions.com Signed-off-by: Dario Binacchi dario.binacchi@amarulasolutions.com ---
drivers/clk/imx/clk-imx8mm.c | 64 +++++++++++++++++++++++++++++------- 1 file changed, 52 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index a91c6767fac5..432348a15cad 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -27,11 +27,25 @@ static const char * const imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", " "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
+#ifndef CONFIG_SPL_BUILD +static const char * const imx8mm_noc_sels[] = {"clock-osc-24m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char * const imx8mm_noc_apb_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll3_out", + "sys_pll2_333m", "sys_pll2_200m", + "sys_pll1_800m", "audio_pll1_out", + "video_pll1_out", }; + static const char * const imx8mm_ahb_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
-#ifndef CONFIG_SPL_BUILD +static const char * const imx8mm_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", + "sys_pll1_800m", "sys_pll2_250m", + "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "sys_pll1_100m",}; + static const char * const imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", }; @@ -47,6 +61,11 @@ static const char * const imx8mm_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2 static const char * const imx8mm_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m", "sys_pll2_500m", "video_pll1_out", "audio_pll2_out", }; + +static const char * const imx8mm_dram_apb_sels[] = {"clock-osc-24m", "sys_pll2_200m", + "sys_pll1_40m", "sys_pll1_160m", + "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; #endif
static const char * const imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", @@ -82,8 +101,9 @@ static const char * const imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m" "audio_pll2_out", "sys_pll1_133m", };
#if CONFIG_IS_ENABLED(PCIE_DW_IMX) -static const char * const imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m", - "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m", +static const char * const imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", + "sys_pll2_200m", "sys_pll1_266m", + "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", };
static const char * const imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m", @@ -135,6 +155,10 @@ static const char * const imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_10 "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", };
+static const char * const imx8mm_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll1_800m", "clk_ext2", + "clk_ext4", "audio_pll2_out" }; + #if CONFIG_IS_ENABLED(DM_SPI) static const char * const imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", @@ -283,18 +307,34 @@ static int imx8mm_clk_probe(struct udevice *dev) imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
- clk_dm(IMX8MM_CLK_AHB, - imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels, - base + 0x9000)); clk_dm(IMX8MM_CLK_IPG_ROOT, imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
+#ifndef CONFIG_SPL_BUILD + /* BUS */ + clk_dm(IMX8MM_CLK_MAIN_AXI, + imx8m_clk_composite_critical("main_axi", + imx8mm_main_axi_sels, base + 0x8800)); + clk_dm(IMX8MM_CLK_ENET_AXI, + imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels, base + 0x8880)); + clk_dm(IMX8MM_CLK_NOC, + imx8m_clk_composite_critical("noc", imx8mm_noc_sels, base + 0x8d00)); + clk_dm(IMX8MM_CLK_NOC_APB, + imx8m_clk_composite_critical("noc_apb", imx8mm_noc_apb_sels, + base + 0x8d80)); + clk_dm(IMX8MM_CLK_AHB, + imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels, base + 0x9000)); + clk_dm(IMX8MM_CLK_DRAM_APB, + imx8m_clk_composite_critical("dram_apb", imx8mm_dram_apb_sels, + base + 0xa080)); +#endif + clk_dm(IMX8MM_CLK_NAND_USDHC_BUS, - imx8m_clk_composite_critical("nand_usdhc_bus", - imx8mm_nand_usdhc_sels, + imx8m_clk_composite_critical("nand_usdhc_bus", imx8mm_nand_usdhc_sels, base + 0x8900)); + clk_dm(IMX8MM_CLK_USB_BUS, - imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80)); + imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
/* IP */ #if CONFIG_IS_ENABLED(PCIE_DW_IMX) @@ -358,9 +398,6 @@ static int imx8mm_clk_probe(struct udevice *dev)
/* clks not needed in SPL stage */ #ifndef CONFIG_SPL_BUILD - clk_dm(IMX8MM_CLK_ENET_AXI, - imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels, - base + 0x8880)); clk_dm(IMX8MM_CLK_ENET_REF, imx8m_clk_composite("enet_ref", imx8mm_enet_ref_sels, base + 0xa980)); @@ -396,6 +433,9 @@ static int imx8mm_clk_probe(struct udevice *dev) imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0)); #endif
+ clk_dm(IMX8MM_CLK_GIC, + imx8m_clk_composite_critical("gic", imx8mm_gic_sels, base + 0xb200)); + #if CONFIG_IS_ENABLED(DM_SPI) clk_dm(IMX8MM_CLK_ECSPI1, imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));