On Tue, Jan 29, 2019 at 11:29 AM Vignesh R vigneshr@ti.com wrote:
Add a tiny SPI flash stack that just supports reading data/images from SPI flash. This is useful for boards that have SPL size constraints and would need to use SPI flash framework just to read images/data from flash. There is approximately 1.5 to 2KB savings with this.
Based on prior work of reducing spi flash id table by Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
Signed-off-by: Vignesh R vigneshr@ti.com Tested-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Tested-by: Stefan Roese sr@denx.de Tested-by: Horatiu Vultur horatiu.vultur@microchip.com
common/spl/Kconfig | 11 +- drivers/mtd/spi/Makefile | 10 +- drivers/mtd/spi/sf_internal.h | 2 + drivers/mtd/spi/spi-nor-core.c | 266 +---------- drivers/mtd/spi/spi-nor-ids.c | 297 ++++++++++++ drivers/mtd/spi/spi-nor-tiny.c | 810 +++++++++++++++++++++++++++++++++ 6 files changed, 1132 insertions(+), 264 deletions(-) create mode 100644 drivers/mtd/spi/spi-nor-ids.c create mode 100644 drivers/mtd/spi/spi-nor-tiny.c
diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 2e1dd2705a62..416f5933b0d9 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -732,9 +732,18 @@ config SPL_SPI_FLASH_SUPPORT
if SPL_SPI_FLASH_SUPPORT
+config SPL_SPI_FLASH_TINY
bool "Enable low footprint SPL SPI Flash support"depends on !SPI_FLASH_BARhelpEnable lightweight SPL SPI Flash support that supports just readingdata/images from flash. No support to write/erase flash. Enablethis if you have SPL size limitations and don't need fullfledged SPI flash support.config SPL_SPI_FLASH_SFDP_SUPPORT bool "SFDP table parsing support for SPI NOR flashes"
depends on !SPI_FLASH_BAR
depends on !SPI_FLASH_BAR && !SPL_SPI_FLASH_TINY help Enable support for parsing and auto discovery of parameters for SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 70058d3df2b9..f99f6cb16e29 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -4,12 +4,20 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o +spi-nor-y := sf_probe.o spi-nor-ids.o
ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o +ifeq ($(CONFIG_SPL_SPI_FLASH_TINY),y) +spi-nor-y += spi-nor-tiny.o +else +spi-nor-y += spi-nor-core.o +endif +else +spi-nor-y += spi-nor-core.o endif
-obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi-nor-core.o +obj-$(CONFIG_SPI_FLASH) += spi-nor.o obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o sf.o obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index fd00e0d1b23b..a6bf734830a7 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -16,7 +16,9 @@ #define SPI_NOR_MAX_ADDR_WIDTH 4
struct flash_info { +#if !CONFIG_IS_ENABLED(SPI_FLASH_TINY) char *name; +#endif
/* * This array stores the ID bytes.diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index dbaaf45c7e1e..80633f8fd070 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -879,284 +879,26 @@ static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) } #endif /* CONFIG_SPI_FLASH_STMICRO */
-/* Used when the "_ext_id" is two bytes at most */ -#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
.id = { \((_jedec_id) >> 16) & 0xff, \((_jedec_id) >> 8) & 0xff, \(_jedec_id) & 0xff, \((_ext_id) >> 8) & 0xff, \(_ext_id) & 0xff, \}, \.id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \.sector_size = (_sector_size), \.n_sectors = (_n_sectors), \.page_size = 256, \.flags = (_flags),-#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
.id = { \((_jedec_id) >> 16) & 0xff, \((_jedec_id) >> 8) & 0xff, \(_jedec_id) & 0xff, \((_ext_id) >> 16) & 0xff, \((_ext_id) >> 8) & 0xff, \(_ext_id) & 0xff, \}, \.id_len = 6, \.sector_size = (_sector_size), \.n_sectors = (_n_sectors), \.page_size = 256, \.flags = (_flags),-/* NOTE: double check command sets and memory organization when you add
- more nor chips. This current list focusses on newer chips, which
- have been converging on command sets which including JEDEC ID.
- All newly added entries should describe *hardware* and should use SECT_4K
- (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
- scenarios excluding small sectors there is config option that can be
- disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
- For historical (and compatibility) reasons (before we got above config) some
- old entries may be missing 4K flag.
- */
-const struct flash_info spi_nor_ids[] = { -#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
/* Atmel -- some are (confusingly) marketed as "DataFlash" */{ "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },{ "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },{ "at45db011d", INFO(0x1f2200, 0, 64 * 1024, 4, SECT_4K) },{ "at45db021d", INFO(0x1f2300, 0, 64 * 1024, 8, SECT_4K) },{ "at45db041d", INFO(0x1f2400, 0, 64 * 1024, 8, SECT_4K) },{ "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },{ "at45db161d", INFO(0x1f2600, 0, 64 * 1024, 32, SECT_4K) },{ "at45db321d", INFO(0x1f2700, 0, 64 * 1024, 64, SECT_4K) },{ "at45db641d", INFO(0x1f2800, 0, 64 * 1024, 128, SECT_4K) },{ "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },-#endif -#ifdef CONFIG_SPI_FLASH_EON /* EON */
/* EON -- en25xxx */{ "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },{ "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },{ "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },{ "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },-#endif -#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
/* GigaDevice */{"gd25q16", INFO(0xc84015, 0, 64 * 1024, 32,SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)},{"gd25q32", INFO(0xc84016, 0, 64 * 1024, 64,SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)},{"gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)},{"gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)},-#endif -#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
/* ISSI */{ "is25lq040b", INFO(0x9d4013, 0, 64 * 1024, 8,SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },{ "is25lp032", INFO(0x9d6016, 0, 64 * 1024, 64, 0) },{ "is25lp064", INFO(0x9d6017, 0, 64 * 1024, 128, 0) },{ "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,SECT_4K | SPI_NOR_DUAL_READ) },{ "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,SECT_4K | SPI_NOR_DUAL_READ) },{ "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },{ "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },{ "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },-#endif -#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
/* Macronix */{ "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },{ "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },{ "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },{ "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },{ "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },{ "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },{ "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },{ "mx25u1635e", INFO(0xc22535, 0, 64 * 1024, 32, SECT_4K) },{ "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },{ "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },{ "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },{ "mx25l1633e", INFO(0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },-#endif
-#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
/* Micron */{ "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },{ "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },{ "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },{ "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },{ "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },-#endif -#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
/* Spansion/Cypress -- single (large) sector size only, at least* for the chips listed here (without boot sectors).*/{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) },{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },{ "s25fl512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },{ "s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },{ "s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },{ "s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },{ "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },{ "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },{ "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },{ "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },{ "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },{ "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },{ "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) },{ "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },-#endif -#ifdef CONFIG_SPI_FLASH_SST /* SST */
/* SST -- large erase sizes are "overlays", "sectors" are 4K */{ "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },{ "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },{ "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },{ "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },{ "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },{ "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },{ "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },{ "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },{ "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },{ "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },{ "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },{ "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },{ "sst26vf064b", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },{ "sst26wf016", INFO(0xbf2651, 0, 64 * 1024, 32, SECT_4K) },{ "sst26wf032", INFO(0xbf2622, 0, 64 * 1024, 64, SECT_4K) },{ "sst26wf064", INFO(0xbf2643, 0, 64 * 1024, 128, SECT_4K) },-#endif -#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
/* ST Microelectronics -- newer production may have feature updates */{ "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },{ "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },{ "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },{ "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },{ "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },{ "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },{ "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },{ "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },{ "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },{ "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },{ "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },-#endif -#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
/* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */{ "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },{ "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },{ "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },{ "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },{ "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },{ "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },{"w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)},{ "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },{ "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },{ "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },{ "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },{ "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },{"w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)},{"w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)},{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },{ "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },{"w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128,SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)},{"w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256,SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)},{ "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },{ "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },{ "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },-#endif -#ifdef CONFIG_SPI_FLASH_XMC
/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */{ "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },{ "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },-#endif
{ },-};
static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) { int tmp; u8 id[SPI_NOR_MAX_ID_LEN]; const struct flash_info *info;
if (!ARRAY_SIZE(spi_nor_ids))return ERR_PTR(-ENODEV);tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); if (tmp < 0) { dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); return ERR_PTR(tmp); }for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {info = &spi_nor_ids[tmp];
info = spi_nor_ids;for (; info->name; info++) { if (info->id_len) { if (!memcmp(info->id, id, info->id_len))
return &spi_nor_ids[tmp];
return info; } }dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", id[0], id[1], id[2]); return ERR_PTR(-ENODEV);
This doesn't look good to me, this change is part of 08/20 and now it removed. better do the same change in 08/20 by adding new file spi-nor-ids.c
And also I still see MODULE_LICENSE, EXPORT_SYMBOL_GPL macros from Linux. please do remove the same.