Dear Henrik Nordström,
This adds support for the Allwinner A10/A13 SoC's. Additionally board support for the dev-boards sun4i/sun5i is added.
Signed-off-by: Tom Cubie tangliang@allwinnertech.com Signed-off-by: Henrik Nordström henrik@henriknordstrom.net Signed-off-by: Stefan Roese sr@denx.de
[..]
+Henrik Nordstrom henrik@henriknordstrom.net
- A13_OLINUXINO ARM V7 (Allwinner A13 SoC)
- A13_MID ARM V7 (Allwinner A13 SoC)
- CUBIEBOARD ARM V7 (Allwinner A10 SoC)
- CUBIEBOARD_512 ARM V7 (Allwinner A10 SoC)
- HACKBERRY ARM V7 (Allwinner A10 SoC)
- MELE_A1000 ARM V7 (Allwinner A10 SoC)
- MINI-X ARM V7 (Allwinner A10 SoC)
- SUN4I ARM V7 (Allwinner A10 SoC)
- SUN4I_SDCON ARM V7 (Allwinner A10 SoC)
- SUN5I ARM V7 (Allwinner A13 SoC)
- SUN5I_SDCON ARM V7 (Allwinner A13 SoC)
You're not adding these boards here yet ...
Kyle Moffett Kyle.D.Moffett@boeing.com
HWW1U1A P2020
[...]
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile new file mode 100644 index 0000000..cbe1015 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/Makefile
[...]
+include $(TOPDIR)/config.mk
+LIB = $(obj)lib$(SOC).o
+SOBJS += reset.o
+COBJS += timer.o +COBJS += dram.o +COBJS += board.o +COBJS += clock.o +COBJS += pinmux.o
COBJS = x.o y.o z.o works just fine
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
+all: $(obj).depend $(LIB)
+$(LIB): $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
[...]
+#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
Why don't you enable them both? What if someone fiddled with them prior to reset?
+} +#endif
[...]
- cfg = readl(&pio->cfg[0] + index);
- cfg &= ~(0xf << offset);
- cfg |= val << offset;
- writel(cfg, &pio->cfg[0] + index);
clrsetbits_le32()
- return 0;
+}
+int sunxi_gpio_get_cfgpin(u32 pin) +{
- u32 cfg;
- u32 bank = GPIO_BANK(pin);
- u32 index = GPIO_CFG_INDEX(pin);
- u32 offset = GPIO_CFG_OFFSET(pin);
- struct sunxi_gpio *pio =
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank];- cfg = readl(&pio->cfg[0] + index);
- cfg >>= offset;
I think you want to put this into drivers/gpio, no?
- return cfg & 0xf;
+}
diff --git a/arch/arm/cpu/armv7/sunxi/reset.S b/arch/arm/cpu/armv7/sunxi/reset.S new file mode 100644 index 0000000..36714e7 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/reset.S
[...]
+#include <asm/arch/cpu.h>
+#define SUNXI_WDOG_CTL 0x01C20C90 +#define SUNXI_WDOG_MODE 0x01C20C94
+.globl sunxi_reset +sunxi_reset:
- ldr r1, =SUNXI_WDOG_MODE
- mov r3, #0x3
- str r3, [r1]
- mov r0, r0
+_loop_forever:
- b _loop_forever
Put this into proper C code.
diff --git a/arch/arm/cpu/armv7/sunxi/timer.c b/arch/arm/cpu/armv7/sunxi/timer.c new file mode 100644 index 0000000..e19df09 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/timer.c @@ -0,0 +1,117 @@
[...]
+/* delay x useconds */
proper kerneldoc all around won't hurt.
+void __udelay(unsigned long usec) +{
- long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
- ulong now, last = READ_TIMER();
- while (tmo > 0) {
now = READ_TIMER();if (now > last) /* normal (non rollover) */tmo -= now - last;else /* rollover */tmo -= TIMER_LOAD_VAL - last + now;last = now;- }
+}
+/*
- This function is derived from PowerPC code (read timebase as long
long). + * On ARM it just returns the timer value.
- */
+unsigned long long get_ticks(void) +{
- return get_timer(0);
+}
[...]