[PATCH v3 0/2] x86: Various fixes to MTRR and FSP codes

At present Intel Crown Bay does not boot. This was caused by various regression issues introduced when supporting FSP2, and some flaws in MTRR codes.

With this series, U-Boot boot again on Intel Crown Bay board.

Changes in v3: - Add the missing header file include

Changes in v2: - Keep programing MTRR to FSP2 only - Move board_final_cleanup() to fsp2 directory

Bin Meng (2): x86: fsp: Don't program MTRR for DRAM for FSP1 x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWARE

arch/x86/lib/fsp/fsp_common.c | 16 ---------------- arch/x86/lib/fsp/fsp_dram.c | 27 +++++++++++++++++++++++---- arch/x86/lib/fsp2/fsp_common.c | 17 +++++++++++++++++ 3 files changed, 40 insertions(+), 20 deletions(-)