On 06/30/2011 11:57 AM, Matthias Weisser wrote:
zmx25 is a board based on imx25 SoC, 64 Megs of LPDDR, 32 Megs of NOR flash, an optional NAND flash.
Hi Matthias,
diff --git a/board/syteco/zmx25/lowlevel_init.S b/board/syteco/zmx25/lowlevel_init.S new file mode 100644 index 0000000..4f3b756
+#include <asm/macro.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/asm-offsets.h>
+.macro init_aips
- write32 IMX_AIPS1_BASE + AIPS_MPR_0_7, 0x77777777
- write32 IMX_AIPS1_BASE + AIPS_MPR_8_15, 0x77777777
- write32 IMX_AIPS2_BASE + AIPS_MPR_0_7, 0x77777777
- write32 IMX_AIPS2_BASE + AIPS_MPR_8_15, 0x77777777
+.endm
+.macro init_max
- write32 IMX_MAX_BASE + MAX_MPR0, 0x43210
- write32 IMX_MAX_BASE + MAX_MPR1, 0x43210
- write32 IMX_MAX_BASE + MAX_MPR2, 0x43210
- write32 IMX_MAX_BASE + MAX_MPR3, 0x43210
- write32 IMX_MAX_BASE + MAX_MPR4, 0x43210
- write32 IMX_MAX_BASE + MAX_SGPCR0, 0x10
- write32 IMX_MAX_BASE + MAX_SGPCR1, 0x10
- write32 IMX_MAX_BASE + MAX_SGPCR2, 0x10
- write32 IMX_MAX_BASE + MAX_SGPCR3, 0x10
- write32 IMX_MAX_BASE + MAX_SGPCR4, 0x10
- write32 IMX_MAX_BASE + MAX_MGPCR0, 0x0
- write32 IMX_MAX_BASE + MAX_MGPCR1, 0x0
- write32 IMX_MAX_BASE + MAX_MGPCR2, 0x0
- write32 IMX_MAX_BASE + MAX_MGPCR3, 0x0
- write32 IMX_MAX_BASE + MAX_MGPCR4, 0x0
+.endm
All these macro are in common with karo/tx25 and you added useful names instead of raw hexadecimal values. This code is not strictly related to the board, but it is part of the processor initialisation.
I am thinking about if we can factorize this stuff. What about to have a file in asm/arch/ that can be included by all i.MX25 boards ?
+/*
- clocks
- */
+.macro init_clocks
- /* disable clock output */
- write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
- write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
- /*
* enable all implemented clocks in all three* clock control registers*/- write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
- write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
- write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
- /* Devide NAND clock by 32 */
- write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
+.endm
The same with this macro, adding maybe a parameter for the different CCTL value.
- /*
* Set up LAN-RESET and FEC_RX_ERR** LAN-RESET: gpio3[16] is ALT 5 mode of pin U20* FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2*/- muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
- padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
- writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk);
- writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
- /* assert PHY reset (low) */
- val = readl(&gpio3->dr) & ~(1 << 16);
- writel(val, &gpio3->dr);
- val = readl(&gpio3->dir) | (1 << 16);
- writel(val, &gpio3->dir);
For i.MX there are accessors to access gpios (mxc_gpio_*). They are not yet extended to the i.MX25, but I see the internal structure is the same as for other i.MX processors. As far as I can see, it should be enough to change the i.MX25 imx-reg-h using the same defines gor GPIO base addresses already used by other microprocessors.
- udelay(5000);
- /* deassert PHY reset */
- val = readl(&gpio3->dr) | 1 << 16;
- writel(val, &gpio3->dr);
The same here. Access to gpios should be fixed globally.
+void dram_init_banksize(void) +{
- gd->bd->bi_dram[0].start = PHYS_SDRAM;
- gd->bd->bi_dram[0].size = gd->ram_size;
+}
You copy the same function that is defined as weak in arch/arm/lib/board.c. You could rely on that function and drop this one.
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
You do not need to set this to 1, it is enough to define it. The same for most of the defines in this file.
Best regards, Stefano Babic