18 May
2022
18 May
'22
5:43 a.m.
On Tue, 17 May 2022 at 03:41, Masahisa Kojima masahisa.kojima@linaro.org wrote:
There is a TX-FIFO and Shift Register empty(TFES) status bit in spi controller. This commit checks the TFES bit to wait the TX transfer completes.
Signed-off-by: Masahisa Kojima masahisa.kojima@linaro.org Signed-off-by: Satoru Okamoto okamoto.satoru@socionext.com
Acked-by: Jassi Brar jaswinder.singh@linaro.org