The DSDT table contains a bytecode that is executed by a driver in the kernel.
Signed-off-by: Saket Sinha saket.sinha89@gmail.com ---
board/intel/minnowmax/Makefile | 2 +- board/intel/minnowmax/acpi/cpu.asl | 65 +++++++ board/intel/minnowmax/acpi/device_nvs.asl | 75 ++++++++ board/intel/minnowmax/acpi/globalnvs.asl | 88 +++++++++ board/intel/minnowmax/acpi/mainboard.asl | 13 ++ board/intel/minnowmax/acpi/platform.asl | 62 ++++++ board/intel/minnowmax/acpi/sleepstates.asl | 14 ++ board/intel/minnowmax/acpi/southcluster.asl | 286 ++++++++++++++++++++++++++++ board/intel/minnowmax/dsdt.asl | 46 +++++ 9 files changed, 650 insertions(+), 1 deletion(-) create mode 100644 board/intel/minnowmax/acpi/cpu.asl create mode 100644 board/intel/minnowmax/acpi/device_nvs.asl create mode 100644 board/intel/minnowmax/acpi/globalnvs.asl create mode 100644 board/intel/minnowmax/acpi/mainboard.asl create mode 100644 board/intel/minnowmax/acpi/platform.asl create mode 100644 board/intel/minnowmax/acpi/sleepstates.asl create mode 100644 board/intel/minnowmax/acpi/southcluster.asl create mode 100644 board/intel/minnowmax/dsdt.asl
diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile index 11f020a..e8d77c8 100644 --- a/board/intel/minnowmax/Makefile +++ b/board/intel/minnowmax/Makefile @@ -5,4 +5,4 @@ #
obj-y += minnowmax.o start.o -obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o diff --git a/board/intel/minnowmax/acpi/cpu.asl b/board/intel/minnowmax/acpi/cpu.asl new file mode 100644 index 0000000..13ca8b9 --- /dev/null +++ b/board/intel/minnowmax/acpi/cpu.asl @@ -0,0 +1,65 @@ +/* + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * From coreboot. + */ + +/* These devices are created at runtime */ +External (_PR.CP00, DeviceObj) +External (_PR.CP01, DeviceObj) +External (_PR.CP02, DeviceObj) +External (_PR.CP03, DeviceObj) + +/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ +Method (PNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (_PR.CP00, 0x81) /* _CST */ + Notify (_PR.CP01, 0x81) /* _CST */ + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (_PR.CP02, 0x81) /* _CST */ + Notify (_PR.CP03, 0x81) /* _CST */ + } +} + +/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ +Method (PPCN) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (_PR.CP00, 0x80) /* _PPC */ + Notify (_PR.CP01, 0x80) /* _PPC */ + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (_PR.CP02, 0x80) /* _PPC */ + Notify (_PR.CP03, 0x80) /* _PPC */ + } +} + +/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ +Method (TNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (_PR.CP00, 0x82) /* _TPC */ + Notify (_PR.CP01, 0x82) /* _TPC */ + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (_PR.CP02, 0x82) /* _TPC */ + Notify (_PR.CP03, 0x82) /* _TPC */ + } +} + +/* Return a package containing enabled processor entries */ +Method (PPKG) +{ + If (LGreaterEqual (\PCNT, 4)) { + Return (Package() {_PR.CP00, _PR.CP01, _PR.CP02, _PR.CP03}) + } ElseIf (LGreaterEqual (\PCNT, 2)) { + Return (Package() {_PR.CP00, _PR.CP01}) + } Else { + Return (Package() {_PR.CP00}) + } +} diff --git a/board/intel/minnowmax/acpi/device_nvs.asl b/board/intel/minnowmax/acpi/device_nvs.asl new file mode 100644 index 0000000..1fd0eb7 --- /dev/null +++ b/board/intel/minnowmax/acpi/device_nvs.asl @@ -0,0 +1,75 @@ +/* + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * From coreboot. + */ + +/* Device Enabled in ACPI Mode */ + +S0EN, 8, /* SDMA Enable */ +S1EN, 8, /* I2C1 Enable */ +S2EN, 8, /* I2C2 Enable */ +S3EN, 8, /* I2C3 Enable */ +S4EN, 8, /* I2C4 Enable */ +S5EN, 8, /* I2C5 Enable */ +S6EN, 8, /* I2C6 Enable */ +S7EN, 8, /* I2C7 Enable */ +S8EN, 8, /* SDMA2 Enable */ +S9EN, 8, /* SPI Enable */ +SAEN, 8, /* PWM1 Enable */ +SBEN, 8, /* PWM2 Enable */ +SCEN, 8, /* UART2 Enable */ +SDEN, 8, /* UART2 Enable */ +C0EN, 8, /* MMC Enable */ +C1EN, 8, /* SDIO Enable */ +C2EN, 8, /* SD Card Enable */ +LPEN, 8, /* LPE Enable */ + +/* BAR 0 */ + +S0B0, 32, /* SDMA BAR0 */ +S1B0, 32, /* I2C1 BAR0 */ +S2B0, 32, /* I2C2 BAR0 */ +S3B0, 32, /* I2C3 BAR0 */ +S4B0, 32, /* I2C4 BAR0 */ +S5B0, 32, /* I2C5 BAR0 */ +S6B0, 32, /* I2C6 BAR0 */ +S7B0, 32, /* I2C7 BAR0 */ +S8B0, 32, /* SDMA2 BAR0 */ +S9B0, 32, /* SPI BAR0 */ +SAB0, 32, /* PWM1 BAR0 */ +SBB0, 32, /* PWM2 BAR0 */ +SCB0, 32, /* UART1 BAR0 */ +SDB0, 32, /* UART2 BAR0 */ +C0B0, 32, /* MMC BAR0 */ +C1B0, 32, /* SDIO BAR0 */ +C2B0, 32, /* SD Card BAR0 */ +LPB0, 32, /* LPE BAR0 */ + +/* BAR 1 */ + +S0B1, 32, /* SDMA BAR1 */ +S1B1, 32, /* I2C1 BAR1 */ +S2B1, 32, /* I2C2 BAR1 */ +S3B1, 32, /* I2C3 BAR1 */ +S4B1, 32, /* I2C4 BAR1 */ +S5B1, 32, /* I2C5 BAR1 */ +S6B1, 32, /* I2C6 BAR1 */ +S7B1, 32, /* I2C7 BAR1 */ +S8B1, 32, /* SDMA2 BAR1 */ +S9B1, 32, /* SPI BAR1 */ +SAB1, 32, /* PWM1 BAR1 */ +SBB1, 32, /* PWM2 BAR1 */ +SCB1, 32, /* UART1 BAR1 */ +SDB1, 32, /* UART2 BAR1 */ +C0B1, 32, /* MMC BAR1 */ +C1B1, 32, /* SDIO BAR1 */ +C2B1, 32, /* SD Card BAR1 */ +LPB1, 32, /* LPE BAR1 */ + +/* Extra */ + +LPFW, 32, /* LPE BAR2 Firmware */ diff --git a/board/intel/minnowmax/acpi/globalnvs.asl b/board/intel/minnowmax/acpi/globalnvs.asl new file mode 100644 index 0000000..5112be8 --- /dev/null +++ b/board/intel/minnowmax/acpi/globalnvs.asl @@ -0,0 +1,88 @@ +/* + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * From coreboot. + */ + + +/* Global Variables */ + +Name(\PICM, 0) /* IOAPIC/8259 */ + +/* Global ACPI memory region */ + +External(NVSA) +OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + Offset (0x00), + OSYS, 16, /* 0x00 - Operating System */ + SMIF, 8, /* 0x02 - SMI function */ + PRM0, 8, /* 0x03 - SMI function parameter */ + PRM1, 8, /* 0x04 - SMI function parameter */ + SCIF, 8, /* 0x05 - SCI function */ + PRM2, 8, /* 0x06 - SCI function parameter */ + PRM3, 8, /* 0x07 - SCI function parameter */ + LCKF, 8, /* 0x08 - Global Lock function for EC */ + PRM4, 8, /* 0x09 - Lock function parameter */ + PRM5, 8, /* 0x0a - Lock function parameter */ + P80D, 32, /* 0x0b - Debug port (IO 0x80) value */ + LIDS, 8, /* 0x0f - LID state (open = 1) */ + PWRS, 8, /* 0x10 - Power State (AC = 1) */ + PCNT, 8, /* 0x11 - Processor count */ + TPMP, 8, /* 0x12 - TPM Present and Enabled + TLVL, 8, /* 0x13 - Throttle Level + PPCM, 8, /* 0x14 - Maximum P-state usable by OS + + /* Device Config */ + Offset (0x20), + S5U0, 8, /* 0x20 - Enable USB0 in S5 */ + S5U1, 8, /* 0x21 - Enable USB1 in S5 */ + S3U0, 8, /* 0x22 - Enable USB0 in S3 */ + S3U1, 8, /* 0x23 - Enable USB1 in S3 */ + TACT, 8, /* 0x24 - Thermal Active trip point */ + TPSV, 8, /* 0x25 - Thermal Passive trip point */ + TCRT, 8, /* 0x26 - Thermal Critical trip point */ + DPTE, 8, /* 0x27 - Enable DPTF */ + + /* Base addresses */ + Offset (0x30), + CMEM, 32, /* 0x30 - CBMEM TOC */ + TOLM, 32, /* 0x34 - Top of Low Memory */ + CBMC, 32, /* 0x38 - coreboot mem console pointer */ + + Offset (0x1000), + #include "device_nvs.asl" +} + +/* Set flag to enable USB charging in S3 */ +Method (S3UE) +{ + Store (One, \S3U0) + Store (One, \S3U1) +} + +/* Set flag to disable USB charging in S3 */ +Method (S3UD) +{ + Store (Zero, \S3U0) + Store (Zero, \S3U1) +} + +/* Set flag to enable USB charging in S5 */ +Method (S5UE) +{ + Store (One, \S5U0) + Store (One, \S5U1) +} + +/* Set flag to disable USB charging in S5 */ +Method (S5UD) +{ + Store (Zero, \S5U0) + Store (Zero, \S5U1) +} diff --git a/board/intel/minnowmax/acpi/mainboard.asl b/board/intel/minnowmax/acpi/mainboard.asl new file mode 100644 index 0000000..95d1a0f --- /dev/null +++ b/board/intel/minnowmax/acpi/mainboard.asl @@ -0,0 +1,13 @@ +/* + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * From coreboot. + */ + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) +} diff --git a/board/intel/minnowmax/acpi/platform.asl b/board/intel/minnowmax/acpi/platform.asl new file mode 100644 index 0000000..cf84194 --- /dev/null +++ b/board/intel/minnowmax/acpi/platform.asl @@ -0,0 +1,62 @@ +/* + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * From coreboot. + */ + + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, /* APM command */ + APMS, 8 /* APM status */ +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice */ + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/board/intel/minnowmax/acpi/sleepstates.asl b/board/intel/minnowmax/acpi/sleepstates.asl new file mode 100644 index 0000000..47bdadf --- /dev/null +++ b/board/intel/minnowmax/acpi/sleepstates.asl @@ -0,0 +1,14 @@ +/* + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * From coreboot. + */ + + +Name(_S0, Package(){0x0,0x0,0x0,0x0}) +Name(_S3, Package(){0x5,0x5,0x0,0x0}) +Name(_S4, Package(){0x6,0x6,0x0,0x0}) +Name(_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/board/intel/minnowmax/acpi/southcluster.asl b/board/intel/minnowmax/acpi/southcluster.asl new file mode 100644 index 0000000..40560c7 --- /dev/null +++ b/board/intel/minnowmax/acpi/southcluster.asl @@ -0,0 +1,286 @@ +/* + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * From coreboot. + */ + +#define ILB_BASE_ADDRESS 0xfed08000 +#define ILB_BASE_SIZE 0x400 +#define MMCONF_BASE_ADDRESS 0xe0000000 + +#define MCFG_BASE_ADDRESS 0xe0000000 +#define MCFG_BASE_SIZE 0x10000000 + +/* Transactions in this range will abort */ +#define ABORT_BASE_ADDRESS 0xfeb00000 +#define ABORT_BASE_SIZE 0x00100000 + +/* Power Management Controller */ +#define PMC_BASE_ADDRESS 0xfed03000 +#define PMC_BASE_SIZE 0x400 + +/* IO Memory */ +#define IO_BASE_ADDRESS 0xfed0c000 +#define IO_BASE_OFFSET_GPSCORE 0x0000 +#define IO_BASE_OFFSET_GPNCORE 0x1000 +#define IO_BASE_OFFSET_GPSSUS 0x2000 +#define IO_BASE_SIZE 0x4000 + +/* Intel Legacy Block */ +#define ILB_BASE_ADDRESS 0xfed08000 +#define ILB_BASE_SIZE 0x400 + +/* SPI Bus */ +#define SPI_BASE_ADDRESS 0xfed01000 +#define SPI_BASE_SIZE 0x400 + +/* MODPHY */ +#define MPHY_BASE_ADDRESS 0xfef00000 +#define MPHY_BASE_SIZE 0x100000 + +/* Power Management Unit */ +#define PUNIT_BASE_ADDRESS 0xfed05000 +#define PUNIT_BASE_SIZE 0x800 + +/* Root Complex Base Address */ +#define RCBA_BASE_ADDRESS 0xfed1c000 +#define RCBA_BASE_SIZE 0x400 + +/* High Performance Event Timer */ +#define HPET_BASE_ADDRESS 0xfed00000 +#define HPET_BASE_SIZE 0x400 + +/* Temporary Base Address */ +#define TEMP_BASE_ADDRESS 0xfd000000 + + + + +Scope() +{ + /* IO-Trap at 0x800. This is the ACPI->SMI communication interface */ + + OperationRegion(IO_T, SystemIO, 0x800, 0x10) + Field(IO_T, ByteAcc, NoLock, Preserve) + { + Offset(0x8), + TRP0, 8 /* IO-Trap at 0x808 */ + } + + /* Intel Legacy Block */ + OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) + Field (ILBS, AnyAcc, NoLock, Preserve) + { + Offset (0x8), + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, + PRTE, 8, + PRTF, 8, + PRTG, 8, + PRTH, 8, + } +} + +Name(_HID,EISAID("PNP0A08")) /* PCIe */ +Name(_CID,EISAID("PNP0A03")) /* PCI */ + +Name(_ADR, 0) +Name(_BBN, 0) + +Name (MCRS, ResourceTemplate() +{ + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + /* OPROM reserved (0xc0000-0xc3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + /* OPROM reserved (0xc4000-0xc7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + /* OPROM reserved (0xc8000-0xcbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + /* OPROM reserved (0xcc000-0xcffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + /* OPROM reserved (0xd0000-0xd3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + /* OPROM reserved (0xd4000-0xd7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + /* OPROM reserved (0xd8000-0xdbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + /* OPROM reserved (0xdc000-0xdffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + /* BIOS Extension (0xe0000-0xe3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + /* BIOS Extension (0xe4000-0xe7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + /* BIOS Extension (0xe8000-0xebfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + /* BIOS Extension (0xec000-0xeffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + /* System BIOS (0xf0000-0xfffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + /* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PMEM) + + /* TPM Area (0xfed40000-0xfed44fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) +}) + + +Method (_CRS, 0, Serialized) +{ + /* Update PCI resource area */ + CreateDwordField(MCRS, ^PMEM._MIN, PMIN) + CreateDwordField(MCRS, ^PMEM._MAX, PMAX) + CreateDwordField(MCRS, ^PMEM._LEN, PLEN) + + /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */ + Store (\TOLM, PMIN) + Store (Subtract(MMCONF_BASE_ADDRESS, 1), PMAX) + Add (Subtract (PMAX, PMIN), 1, PLEN) + + Return (MCRS) +} + +/* Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + + Name (PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) + Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) + Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) + Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) + Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) + Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE) + Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE) + Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) + }) + + /* Current Resource Settings */ + Method (_CRS, 0, Serialized) + { + Return(PDRS) + } +} + +Method (_OSC, 4) +{ + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + Else + { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } +} + +/* IOSF MBI Interface for kernel access */ +Device (IOSF) +{ + Name (_HID, "INT33BD") + Name (_CID, "INT33BD") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + /* MCR / MDR / MCRX */ + Memory32Fixed (ReadWrite, 0, 12, RBAR) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^RBAR._BAS, RBAS) + Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS) + Return (^RBUF) + } +} + diff --git a/board/intel/minnowmax/dsdt.asl b/board/intel/minnowmax/dsdt.asl new file mode 100644 index 0000000..4fac14c --- /dev/null +++ b/board/intel/minnowmax/dsdt.asl @@ -0,0 +1,46 @@ +/* + * Minnowmax ACPI DSDT ASL definition + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * Based on baytrail/dsdt.asl from coreboot + */ + +#define INCLUDE_LPE 1 +#define INCLUDE_SCC 1 +#define INCLUDE_EHCI 1 +#define INCLUDE_XHCI 1 +#define INCLUDE_LPSS 1 + + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 */ + "COREv4", /* OEM id */ + "UBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + + /* global NVS and variables */ + #include "acpi/globalnvs.asl" + + #include "acpi/cpu.asl" + + Scope (_SB) { + Device (PCI0) + { + #include "acpi/southcluster.asl" + } + } + /* Chipset specific sleep states */ + #include "acpi/sleepstates.asl" + + #include "acpi/mainboard.asl" +} +