From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Up to now, there are 3 kinds of SoC under Layerscape Chassis 2, such as LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of difference, for instance the IP modules have different divisors to get clock from Platform PLL. And the core cluster and platform PLL maybe have different reference clock, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Chissis 2.
This patch is to map the sys_info->freq_systembus to the Platform PLL, and handle the different divisor of IP modules separately between different SoCs. And separate cluster and platform PLL reference clock.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Generate the patch set base on the latest git://git.denx.de/u-boot-fsl-qoriq.git. - Show Platform clock as Bus frequency. - Add Platform clock and IPs' input clock divisors.
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 71 ++++++++++++++++------ arch/arm/include/asm/arch-fsl-layerscape/config.h | 26 ++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + include/configs/ls1012a_common.h | 6 +- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 2 +- 7 files changed, 87 insertions(+), 24 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 5fbd848..4811f1f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -315,8 +315,9 @@ int print_cpuinfo(void) (type == TY_ITYP_VER_A72 ? "A72" : " "))), strmhz(buf, sysinfo.freq_processor[core])); } + /* Display platform clock as Bus frequency. */ printf("\n Bus: %-4s MHz ", - strmhz(buf, sysinfo.freq_systembus)); + strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV)); printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); #ifdef CONFIG_SYS_DPAA_FMAN printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0])); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 8922197..4b6863d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -52,22 +52,28 @@ void get_sys_info(struct sys_info *sys_info) uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + unsigned long cluster_clk;
sys_info->freq_systembus = sysclk; +#ifndef CONFIG_CLUSTER_CLK_FREQ +#define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ +#endif + cluster_clk = CONFIG_CLUSTER_CLK_FREQ; + #ifdef CONFIG_DDR_CLK_FREQ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; #else sys_info->freq_ddrbus = sysclk; #endif
-#ifdef CONFIG_LS1012A - sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> - FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & - FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; -#else + /* The freq_systembus is used to record frequency of platform PLL */ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) & FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK; + +#ifdef CONFIG_LS1012A + sys_info->freq_ddrbus = 2 * sys_info->freq_systembus; +#else sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK; @@ -76,7 +82,7 @@ void get_sys_info(struct sys_info *sys_info) for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) { ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff; if (ratio[i] > 4) - freq_c_pll[i] = sysclk * ratio[i]; + freq_c_pll[i] = cluster_clk * ratio[i]; else freq_c_pll[i] = sys_info->freq_systembus * ratio[i]; } @@ -91,11 +97,6 @@ void get_sys_info(struct sys_info *sys_info) freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; }
-#ifdef CONFIG_LS1012A - sys_info->freq_systembus = sys_info->freq_ddrbus / 2; - sys_info->freq_ddrbus *= 2; -#endif - #define HWA_CGA_M1_CLK_SEL 0xe0000000 #define HWA_CGA_M1_CLK_SHIFT 29 #ifdef CONFIG_SYS_DPAA_FMAN @@ -148,7 +149,8 @@ void get_sys_info(struct sys_info *sys_info) break; } #else - sys_info->freq_sdhc = sys_info->freq_systembus; + sys_info->freq_sdhc = sys_info->freq_systembus / + CONFIG_SYS_FSL_SDHC_CLK_DIV; #endif #endif
@@ -156,7 +158,8 @@ void get_sys_info(struct sys_info *sys_info) ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
- sys_info->freq_localbus = sys_info->freq_systembus / ccr; + sys_info->freq_localbus = sys_info->freq_systembus / + CONFIG_SYS_FSL_PCLK_DIV / ccr; #endif }
@@ -166,7 +169,7 @@ int get_clocks(void)
get_sys_info(&sys_info); gd->cpu_clk = sys_info.freq_processor[0]; - gd->bus_clk = sys_info.freq_systembus; + gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV; gd->mem_clk = sys_info.freq_ddrbus;
#ifdef CONFIG_FSL_ESDHC @@ -179,41 +182,73 @@ int get_clocks(void) return 1; }
+/******************************************** + * get_bus_freq + * return platform clock in Hz + *********************************************/ ulong get_bus_freq(ulong dummy) { + if (!gd->bus_clk) + get_clocks(); + return gd->bus_clk; }
ulong get_ddr_freq(ulong dummy) { + if (!gd->mem_clk) + get_clocks(); + return gd->mem_clk; }
#ifdef CONFIG_FSL_ESDHC int get_sdhc_freq(ulong dummy) { + if (!gd->arch.sdhc_clk) + get_clocks(); + return gd->arch.sdhc_clk; } #endif
int get_serial_clock(void) { - return gd->bus_clk; + return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; +} + +int get_i2c_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV; +} + +int get_dspi_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV; }
+#ifdef CONFIG_FSL_LPUART +int get_uart_freq(ulong dummy) +{ + return get_bus_freq(0) / CONFIG_SYS_FSL_LPUART_CLK_DIV; +} +#endif + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { case MXC_I2C_CLK: - return get_bus_freq(0); + return get_i2c_freq(0); #if defined(CONFIG_FSL_ESDHC) case MXC_ESDHC_CLK: return get_sdhc_freq(0); #endif case MXC_DSPI_CLK: - return get_bus_freq(0); + return get_dspi_freq(0); +#ifdef CONFIG_FSL_LPUART case MXC_UART_CLK: - return get_bus_freq(0); + return get_uart_freq(0); +#endif default: printf("Unsupported clock\n"); } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 81a5e7c..bc0af99 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -183,6 +183,15 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+/* Platform PLL frequency divisor for platform clock */ +#define CONFIG_SYS_FSL_PCLK_DIV 1 +/* Platform clock divisor for IPs' input clock */ +#define CONFIG_SYS_FSL_DUART_CLK_DIV 1 +#define CONFIG_SYS_FSL_I2C_CLK_DIV 1 +#define CONFIG_SYS_FSL_DSPI_CLK_DIV 1 +#define CONFIG_SYS_FSL_LPUART_CLK_DIV 1 +#define CONFIG_SYS_FSL_SDHC_CLK_DIV 1 + #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 @@ -211,6 +220,14 @@ #define CONFIG_MAX_CPUS 1 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
+/* Platform PLL frequency divisor for platform clock */ +#define CONFIG_SYS_FSL_PCLK_DIV 2 +/* Platform clock divisor for IPs' input clock */ +#define CONFIG_SYS_FSL_DUART_CLK_DIV 2 +#define CONFIG_SYS_FSL_I2C_CLK_DIV 2 +#define CONFIG_SYS_FSL_DSPI_CLK_DIV 2 +#define CONFIG_SYS_FSL_SDHC_CLK_DIV 2 + #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 #elif defined(CONFIG_LS1046A) @@ -224,6 +241,15 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
+/* Platform PLL frequency divisor for platform clock */ +#define CONFIG_SYS_FSL_PCLK_DIV 1 +/* Platform clock divisor for IPs' input clock */ +#define CONFIG_SYS_FSL_DUART_CLK_DIV 2 +#define CONFIG_SYS_FSL_I2C_CLK_DIV 2 +#define CONFIG_SYS_FSL_DSPI_CLK_DIV 2 +#define CONFIG_SYS_FSL_LPUART_CLK_DIV 2 +#define CONFIG_SYS_FSL_SDHC_CLK_DIV 2 + #define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_IFC_BE #define CONFIG_SYS_FSL_SFP_VER_3_2 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 95a4293..ee10765 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -136,6 +136,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; + /* frequency of platform PLL */ unsigned long freq_systembus; unsigned long freq_ddrbus; unsigned long freq_localbus; diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index fba2fac..928fd76 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -24,8 +24,8 @@ #define CONFIG_SYS_TEXT_BASE 0x40100000
#define CONFIG_SYS_FSL_CLK -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 125000000 +#define CONFIG_SYS_CLK_FREQ 125000000 +#define CONFIG_CLUSTER_CLK_FREQ 100000000
#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F 1 @@ -86,7 +86,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index e55fcb2..3b55699 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -50,7 +50,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 5856de8..a538742 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -46,7 +46,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }