Add apis to set and get divider clock ratio for FSYS_BLK on EXYNOS5.
Signed-off-by: Terry Lambert tlambert@chromium.org Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com --- arch/arm/cpu/armv7/exynos/clock.c | 96 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 4 + 2 files changed, 100 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 3b86b0c..3af1aac 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -414,6 +414,90 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); }
+static unsigned long exynos5_get_mshci_clk_div(enum periph_id peripheral) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + u32 *addr; + unsigned int div_mmc, div_mmc_pre; + unsigned int mpll_clock, sclk_mmc; + + mpll_clock = get_pll_clk(MPLL); + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0] + * CLK_DIV_FSYS3 + * MMC4_PRE_RATIO [15:8], MMC4_RATIO [3:0] + */ + switch (peripheral) { + case PERIPH_ID_SDMMC0: + addr = &clk->div_fsys1; + break; + case PERIPH_ID_SDMMC2: + addr = &clk->div_fsys2; + break; + case PERIPH_ID_SDMMC4: + addr = &clk->div_fsys3; + break; + default: + debug("invalid peripheral\n"); + return -1; + } + + div_mmc = (readl(addr) & 0xf) + 1; + div_mmc_pre = ((readl(addr) & 0xff00) >> 8) + 1; + sclk_mmc = (mpll_clock / div_mmc) / div_mmc_pre; + + return sclk_mmc; +} + +static int exynos5_set_mshci_clk_div(enum periph_id peripheral) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + u32 *addr; + unsigned int clock; + unsigned int tmp; + unsigned int i; + + /* get mpll clock */ + clock = get_pll_clk(MPLL) / 1000000; + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0] + * CLK_DIV_FSYS3 + * MMC4_PRE_RATIO [15:8], MMC4_RATIO [3:0] + */ + switch (peripheral) { + case PERIPH_ID_SDMMC0: + addr = &clk->div_fsys1; + break; + case PERIPH_ID_SDMMC2: + addr = &clk->div_fsys2; + break; + case PERIPH_ID_SDMMC4: + addr = &clk->div_fsys3; + break; + default: + debug("invalid peripheral\n"); + return -1; + } + tmp = readl(addr) & ~0xff0f; + for (i = 0; i <= 0xf; i++) { + if ((clock / (i + 1)) <= 400) { + writel(tmp | i << 0, addr); + break; + } + } + return 0; +} + /* get_lcd_clk: return lcd clock frequency */ static unsigned long exynos4_get_lcd_clk(void) { @@ -651,6 +735,18 @@ void set_mmc_clk(int dev_index, unsigned int div) exynos4_set_mmc_clk(dev_index, div); }
+unsigned long get_mshci_clk_div(enum periph_id peripheral) +{ + if (cpu_is_exynos5()) + return exynos5_get_mshci_clk_div(peripheral); +} + +int set_mshci_clk_div(enum periph_id peripheral) +{ + if (cpu_is_exynos5()) + return exynos5_set_mshci_clk_div(peripheral); +} + unsigned long get_lcd_clk(void) { if (cpu_is_exynos4()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 72dc655..4a6fa90 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -22,6 +22,8 @@ #ifndef __ASM_ARM_ARCH_CLK_H_ #define __ASM_ARM_ARCH_CLK_H_
+#include <asm/arch/pinmux.h> + #define APLL 0 #define MPLL 1 #define EPLL 2 @@ -34,6 +36,8 @@ unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div); +unsigned long get_mshci_clk_div(enum periph_id peripheral); +int set_mshci_clk_div(enum periph_id peripheral); unsigned long get_lcd_clk(void); void set_lcd_clk(void); void set_mipi_clk(void);