[PATCH v2 01/16] imx7ulp: synchronise device tree with linux

From: Marcel Ziswiler marcel.ziswiler@toradex.com

Synchronise device tree with linux v6.0-rc1.

Signed-off-by: Marcel Ziswiler marcel.ziswiler@toradex.com ---

(no changes since v1)

arch/arm/dts/imx7ulp-com-u-boot.dtsi | 2 +- arch/arm/dts/imx7ulp-com.dts | 32 +- arch/arm/dts/imx7ulp-evk.dts | 430 ++-------- arch/arm/dts/imx7ulp-pinfunc.h | 990 +++++++--------------- arch/arm/dts/imx7ulp.dtsi | 681 ++++++--------- include/dt-bindings/clock/imx7ulp-clock.h | 170 ++-- 6 files changed, 694 insertions(+), 1611 deletions(-)

diff --git a/arch/arm/dts/imx7ulp-com-u-boot.dtsi b/arch/arm/dts/imx7ulp-com-u-boot.dtsi index d73bfbf7a0..b766c5ef3f 100644 --- a/arch/arm/dts/imx7ulp-com-u-boot.dtsi +++ b/arch/arm/dts/imx7ulp-com-u-boot.dtsi @@ -32,6 +32,6 @@ u-boot,dm-spl; };

-&gpio0 { +&gpio_ptc { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imx7ulp-com.dts b/arch/arm/dts/imx7ulp-com.dts index dcfa37441f..d76fea3b35 100644 --- a/arch/arm/dts/imx7ulp-com.dts +++ b/arch/arm/dts/imx7ulp-com.dts @@ -1,12 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 // // Copyright 2019 NXP -// Author: Fabio Estevam fabio.estevam@nxp.com

/dts-v1/;

#include "imx7ulp.dtsi" -#include "imx7ulp-com-u-boot.dtsi" +#include <dt-bindings/input/input.h>

/ { model = "Embedded Artists i.MX7ULP COM"; @@ -16,9 +15,9 @@ stdout-path = &lpuart4; };

- memory { + memory@60000000 { device_type = "memory"; - reg = <0x60000000 0x8000000>; + reg = <0x60000000 0x4000000>; }; };

@@ -37,11 +36,9 @@ status = "okay"; };

-&usbphy1 { - fsl,tx-d-cal = <88>; -}; - &usdhc0 { + assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc0>; non-removable; @@ -51,19 +48,16 @@ };

&iomuxc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_1>; - - pinctrl_hog_1: hoggrp-1 { + pinctrl_lpuart4: lpuart4grp { fsl,pins = < - IMX7ULP_PAD_PTC1__PTC1 0x20000 + IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 + IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 >; };

- pinctrl_lpuart4: lpuart4grp { + pinctrl_usbotg1_id: otg1idgrp { fsl,pins = < - IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 - IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 + IMX7ULP_PAD_PTC13__USB0_ID 0x10003 >; };

@@ -82,10 +76,4 @@ IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 >; }; - - pinctrl_usbotg1_id: otg1idgrp { - fsl,pins = < - IMX7ULP_PAD_PTC13__USB0_ID 0x10003 - >; - }; }; diff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts index 8f6a935e24..eff51e113d 100644 --- a/arch/arm/dts/imx7ulp-evk.dts +++ b/arch/arm/dts/imx7ulp-evk.dts @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright 2017-2018 NXP + * Dong Aisheng aisheng.dong@nxp.com */

/dts-v1/; @@ -12,365 +11,57 @@

/ { model = "NXP i.MX7ULP EVK"; - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system"; + compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";

chosen { - bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200"; stdout-path = &lpuart4; };

- bcmdhd_wlan_0: bcmdhd_wlan@0 { - compatible = "android,bcmdhd_wlan"; - wlreg_on-supply = <&wlreg_on>; - bcmdhd_fw = "/lib/firmware/bcm/1DX_BCM4343W/fw_bcmdhd.bin"; - bcmdhd_nv = "/lib/firmware/bcm/1DX_BCM4343W/bcmdhd.1DX.SDIO.cal"; - }; - - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x40000000>; };

backlight { - compatible = "gpio-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_backlight>; - gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; - default-on; + compatible = "pwm-backlight"; + pwms = <&tpm4 1 50000 0>; + brightness-levels = <0 20 25 30 35 40 100>; + default-brightness-level = <6>; status = "okay"; };

- mipi_dsi_reset: mipi-dsi-reset { - compatible = "gpio-reset"; - reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; - reset-delay-us = <1000>; - #reset-cells = <0>; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - wlreg_on: fixedregulator@100 { - compatible = "regulator-fixed"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "wlreg_on"; - gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; - enable-active-high; - }; - - reg_usb_otg1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1_vbus>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vsd_3v3: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - }; - - pf1550-rpmsg { - compatible = "fsl,pf1550-rpmsg"; - sw1_reg: SW1 { - regulator-name = "SW1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1387500>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: SW2 { - regulator-name = "SW2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1387500>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: SW3 { - regulator-name = "SW3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: VREFDDR { - regulator-name = "VREFDDR"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - vldo1_reg: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vldo2_reg: LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vldo3_reg: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&iomuxc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_1>; - - imx7ulp-evk { - pinctrl_hog_1: hoggrp-1 { - fsl,pins = < - IMX7ULP_PAD_PTC1__PTC1 0x20000 - >; - }; - - pinctrl_backlight: backlight_grp { - fsl,pins = < - IMX7ULP_PAD_PTF2__PTF2 0x20000 - >; - }; - - pinctrl_lpi2c5: lpi2c5grp { - fsl,pins = < - IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x27 - IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x27 - >; - }; - - pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { - fsl,pins = < - IMX7ULP_PAD_PTC19__PTC19 0x20003 - >; - }; - - pinctrl_lpuart4: lpuart4grp { - fsl,pins = < - IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 - IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 - >; - }; - - pinctrl_lpuart6: lpuart6grp { - fsl,pins = < - IMX7ULP_PAD_PTE10__LPUART6_TX 0x3 - IMX7ULP_PAD_PTE11__LPUART6_RX 0x3 - IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x3 - IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x3 - IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */ - >; - }; - - pinctrl_lpuart7: lpuart7grp { - fsl,pins = < - IMX7ULP_PAD_PTF14__LPUART7_TX 0x3 - IMX7ULP_PAD_PTF15__LPUART7_RX 0x3 - IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x3 - IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x3 - >; - }; - - pinctrl_usdhc0: usdhc0grp { - fsl,pins = < - IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 - IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 - IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 - IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 - IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 - IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 - IMX7ULP_PAD_PTC10__PTC10 0x10000 /* USDHC0 CD */ - IMX7ULP_PAD_PTD0__PTD0 0x20000 /* USDHC0 RST */ - >; - }; - - pinctrl_usdhc0_8bit: usdhc0grp_8bit { - fsl,pins = < - IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 - IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 - IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 - IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 - IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 - IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 - IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 - IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 - IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 - IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 - IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 - >; - }; - - pinctrl_lpi2c7: lpi2c7grp { - fsl,pins = < - IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x27 - IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x27 - >; - }; - - pinctrl_lpspi3: lpspi3grp { - fsl,pins = < - IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0 - IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0 - IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0 - IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0 - >; - }; - - pinctrl_usbotg1_vbus: otg1vbusgrp { - fsl,pins = < - IMX7ULP_PAD_PTC0__PTC0 0x20000 - >; - }; - - pinctrl_usbotg1_id: otg1idgrp { - fsl,pins = < - IMX7ULP_PAD_PTC13__USB0_ID 0x10003 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - IMX7ULP_PAD_PTE3__SDHC1_CMD 0x43 - IMX7ULP_PAD_PTE2__SDHC1_CLK 0x10042 - IMX7ULP_PAD_PTE1__SDHC1_D0 0x43 - IMX7ULP_PAD_PTE0__SDHC1_D1 0x43 - IMX7ULP_PAD_PTE5__SDHC1_D2 0x43 - IMX7ULP_PAD_PTE4__SDHC1_D3 0x43 - >; - }; - - pinctrl_usdhc1_rst: usdhc1grp_rst { - fsl,pins = < - IMX7ULP_PAD_PTE11__PTE11 0x20000 /* USDHC1 RST */ - IMX7ULP_PAD_PTE13__PTE13 0x10003 /* USDHC1 CD */ - IMX7ULP_PAD_PTE12__PTE12 0x10003 /* USDHC1 WP */ - IMX7ULP_PAD_PTE14__SDHC1_VS 0x43 /* USDHC1 VSEL */ - >; - }; - - pinctrl_dsi_hdmi: dsi_hdmi_grp { - fsl,pins = < - IMX7ULP_PAD_PTC18__PTC18 0x10003 /* DSI_HDMI_INT */ - >; - }; - }; -}; - -&lcdif { - status = "okay"; - disp-dev = "mipi_dsi_northwest"; - display = <&display0>; - - display0: display@0 { - bits-per-pixel = <16>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9200000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <8>; - hback-porch = <4>; - hsync-len = <41>; - vback-porch = <2>; - vfront-porch = <4>; - vsync-len = <10>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>; + enable-active-high; }; -}; - -&lpi2c7 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c7>; -}; - -&lpi2c5 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c5>; - status = "okay"; -};

-&lpspi3 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpspi3>; - status = "okay"; - - spidev0: spi@0 { - reg = <0>; - compatible = "rohm,dh2228fv"; - spi-max-frequency = <1000000>; + reg_vsd_3v3: regulator-vsd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc0_rst>; + gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>; + enable-active-high; }; };

-&mipi_dsi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mipi_dsi_reset>; - lcd_panel = "TRULY-WVGA-TFT3P5581E"; - resets = <&mipi_dsi_reset>; - status = "okay"; -}; - -&lpuart4 { /* console */ +&lpuart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart4>; status = "okay"; };

-&lpuart6 { /* BT */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart6>; - status = "okay"; -}; - -&lpuart7 { /* Uart test */ +&tpm4 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart7>; - status = "disabled"; -}; - -&rpmsg{ + pinctrl-0 = <&pinctrl_pwm0>; status = "okay"; };

@@ -381,21 +72,62 @@ srp-disable; hnp-disable; adp-disable; + disable-over-current; status = "okay"; };

-&usbphy1 { - fsl,tx-d-cal = <88>; -}; - &usdhc0 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc0>; - pinctrl-1 = <&pinctrl_usdhc0>; - pinctrl-2 = <&pinctrl_usdhc0>; - pinctrl-3 = <&pinctrl_usdhc0>; - cd-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>; vmmc-supply = <&reg_vsd_3v3>; - vqmmc-supply = <&vldo2_reg>; status = "okay"; }; + +&iomuxc1 { + pinctrl_lpuart4: lpuart4grp { + fsl,pins = < + IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 + IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 + >; + bias-pull-up; + }; + + pinctrl_pwm0: pwm0grp { + fsl,pins = < + IMX7ULP_PAD_PTF2__TPM4_CH1 0x2 + >; + }; + + pinctrl_usbotg1_vbus: otg1vbusgrp { + fsl,pins = < + IMX7ULP_PAD_PTC0__PTC0 0x20000 + >; + }; + + pinctrl_usbotg1_id: otg1idgrp { + fsl,pins = < + IMX7ULP_PAD_PTC13__USB0_ID 0x10003 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 + IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40 + IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 + IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 + IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 + IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 + IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */ + >; + }; + + pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp { + fsl,pins = < + IMX7ULP_PAD_PTD0__PTD0 0x3 + >; + }; +}; diff --git a/arch/arm/dts/imx7ulp-pinfunc.h b/arch/arm/dts/imx7ulp-pinfunc.h index 777d7f0947..c0148d79b6 100644 --- a/arch/arm/dts/imx7ulp-pinfunc.h +++ b/arch/arm/dts/imx7ulp-pinfunc.h @@ -1,11 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright 2016 Freescale Semiconductor, Inc. - * Copyright 2017 - 2018 NXP - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * + * Copyright 2017 NXP */

#ifndef __DTS_IMX7ULP_PINFUNC_H @@ -15,654 +11,244 @@ * The pin function ID is a tuple of * <mux_conf_reg input_reg mux_mode input_val> */ -#define IMX7ULP_PAD_PTA0__CMP0_IN1_3V 0x0000 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA0__PTA0 0x0000 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA0__LPSPI0_PCS1 0x0000 0x0104 0x3 0x2 -#define IMX7ULP_PAD_PTA0__LPUART0_CTS_B 0x0000 0x01F8 0x4 0x2 -#define IMX7ULP_PAD_PTA0__LPI2C0_SCL 0x0000 0x017C 0x5 0x2 -#define IMX7ULP_PAD_PTA0__TPM0_CLKIN 0x0000 0x01A8 0x6 0x2 -#define IMX7ULP_PAD_PTA0__I2S0_RX_BCLK 0x0000 0x01B8 0x7 0x2 -#define IMX7ULP_PAD_PTA0__LLWU0_P0 0x0000 0x0000 0xd 0x0 -#define IMX7ULP_PAD_PTA1__CMP0_IN2_3V 0x0004 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA1__LPSPI0_PCS2 0x0004 0x0108 0x3 0x1 -#define IMX7ULP_PAD_PTA1__LPUART0_RTS_B 0x0004 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTA1__LPI2C0_SDA 0x0004 0x0180 0x5 0x1 -#define IMX7ULP_PAD_PTA1__TPM0_CH0 0x0004 0x0138 0x6 0x1 -#define IMX7ULP_PAD_PTA1__I2S0_RX_FS 0x0004 0x01BC 0x7 0x1 -#define IMX7ULP_PAD_PTA2__CMP1_IN2_3V 0x0008 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA2__PTA2 0x0008 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA2__LPSPI0_PCS3 0x0008 0x010C 0x3 0x1 -#define IMX7ULP_PAD_PTA2__LPUART0_TX 0x0008 0x0200 0x4 0x1 -#define IMX7ULP_PAD_PTA2__LPI2C0_HREQ 0x0008 0x0178 0x5 0x1 -#define IMX7ULP_PAD_PTA2__TPM0_CH1 0x0008 0x013C 0x6 0x1 -#define IMX7ULP_PAD_PTA2__I2S0_RXD0 0x0008 0x01DC 0x7 0x1 -#define IMX7ULP_PAD_PTA3__CMP1_IN4_3V 0x000C 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA3__PTA3 0x000C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA3__LPSPI0_PCS0 0x000C 0x0100 0x3 0x1 -#define IMX7ULP_PAD_PTA3__LPUART0_RX 0x000C 0x01FC 0x4 0x1 -#define IMX7ULP_PAD_PTA3__TPM0_CH2 0x000C 0x0140 0x6 0x1 -#define IMX7ULP_PAD_PTA3__I2S0_RXD1 0x000C 0x01E0 0x7 0x1 -#define IMX7ULP_PAD_PTA3__CMP0_OUT 0x000C 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTA3__LLWU0_P1 0x000C 0x0000 0xd 0x0 -#define IMX7ULP_PAD_PTA4__ADC1_CH3A 0x0010 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA4__PTA4 0x0010 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA4__LPSPI0_SIN 0x0010 0x0114 0x3 0x1 -#define IMX7ULP_PAD_PTA4__LPUART1_CTS_B 0x0010 0x0204 0x4 0x1 -#define IMX7ULP_PAD_PTA4__LPI2C1_SCL 0x0010 0x0188 0x5 0x1 -#define IMX7ULP_PAD_PTA4__TPM0_CH3 0x0010 0x0144 0x6 0x1 -#define IMX7ULP_PAD_PTA4__I2S0_MCLK 0x0010 0x01B4 0x7 0x1 -#define IMX7ULP_PAD_PTA5__ADC1_CH3B 0x0014 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA5__PTA5 0x0014 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA5__LPSPI0_SOUT 0x0014 0x0118 0x3 0x1 -#define IMX7ULP_PAD_PTA5__LPUART1_RTS_B 0x0014 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTA5__LPI2C1_SDA 0x0014 0x018C 0x5 0x1 -#define IMX7ULP_PAD_PTA5__TPM0_CH4 0x0014 0x0148 0x6 0x1 -#define IMX7ULP_PAD_PTA5__I2S0_TX_BCLK 0x0014 0x01C0 0x7 0x1 -#define IMX7ULP_PAD_PTA6__ADC1_CH4A 0x0018 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA6__PTA6 0x0018 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA6__LPSPI0_SCK 0x0018 0x0110 0x3 0x1 -#define IMX7ULP_PAD_PTA6__LPUART1_TX 0x0018 0x020C 0x4 0x1 -#define IMX7ULP_PAD_PTA6__LPI2C1_HREQ 0x0018 0x0184 0x5 0x1 -#define IMX7ULP_PAD_PTA6__TPM0_CH5 0x0018 0x014C 0x6 0x1 -#define IMX7ULP_PAD_PTA6__I2S0_TX_FS 0x0018 0x01C4 0x7 0x1 -#define IMX7ULP_PAD_PTA7__ADC1_CH4B 0x001C 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA7__PTA7 0x001C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA7__LPUART1_RX 0x001C 0x0208 0x4 0x1 -#define IMX7ULP_PAD_PTA7__TPM1_CH1 0x001C 0x0154 0x6 0x1 -#define IMX7ULP_PAD_PTA7__I2S0_TXD0 0x001C 0x0000 0x7 0x0 -#define IMX7ULP_PAD_PTA8__ADC1_CH5A 0x0020 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA8__PTA8 0x0020 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA8__LPSPI1_PCS1 0x0020 0x0120 0x3 0x1 -#define IMX7ULP_PAD_PTA8__LPUART2_CTS_B 0x0020 0x0210 0x4 0x1 -#define IMX7ULP_PAD_PTA8__LPI2C2_SCL 0x0020 0x0194 0x5 0x1 -#define IMX7ULP_PAD_PTA8__TPM1_CLKIN 0x0020 0x01AC 0x6 0x1 -#define IMX7ULP_PAD_PTA8__I2S0_TXD1 0x0020 0x0000 0x7 0x0 -#define IMX7ULP_PAD_PTA9__ADC1_CH5B 0x0024 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA9__PTA9 0x0024 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA9__LPSPI1_PCS2 0x0024 0x0124 0x3 0x1 -#define IMX7ULP_PAD_PTA9__LPUART2_RTS_B 0x0024 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTA9__LPI2C2_SDA 0x0024 0x0198 0x5 0x1 -#define IMX7ULP_PAD_PTA9__TPM1_CH0 0x0024 0x0150 0x6 0x1 -#define IMX7ULP_PAD_PTA9__NMI0_B 0x0024 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTA10__ADC1_CH6A 0x0028 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA10__PTA10 0x0028 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA10__LPSPI1_PCS3 0x0028 0x0128 0x3 0x1 -#define IMX7ULP_PAD_PTA10__LPUART2_TX 0x0028 0x0218 0x4 0x1 -#define IMX7ULP_PAD_PTA10__LPI2C2_HREQ 0x0028 0x0190 0x5 0x1 -#define IMX7ULP_PAD_PTA10__TPM2_CLKIN 0x0028 0x01F4 0x6 0x1 -#define IMX7ULP_PAD_PTA10__I2S0_RX_BCLK 0x0028 0x01B8 0x7 0x1 -#define IMX7ULP_PAD_PTA11__ADC1_CH6B 0x002C 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA11__PTA11 0x002C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA11__LPUART2_RX 0x002C 0x0214 0x4 0x1 -#define IMX7ULP_PAD_PTA11__TPM2_CH0 0x002C 0x0158 0x6 0x1 -#define IMX7ULP_PAD_PTA11__I2S0_RX_FS 0x002C 0x01BC 0x7 0x2 -#define IMX7ULP_PAD_PTA12__ADC1_CH7A 0x0030 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA12__PTA12 0x0030 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA12__LPSPI1_SIN 0x0030 0x0130 0x3 0x1 -#define IMX7ULP_PAD_PTA12__LPUART3_CTS_B 0x0030 0x021C 0x4 0x1 -#define IMX7ULP_PAD_PTA12__LPI2C3_SCL 0x0030 0x01A0 0x5 0x1 -#define IMX7ULP_PAD_PTA12__TPM2_CH1 0x0030 0x015C 0x6 0x1 -#define IMX7ULP_PAD_PTA12__I2S0_RXD0 0x0030 0x01DC 0x7 0x2 -#define IMX7ULP_PAD_PTA13__ADC1_CH7B 0x0034 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA13__PTA13 0x0034 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA13__LPSPI1_SOUT 0x0034 0x0134 0x3 0x2 -#define IMX7ULP_PAD_PTA13__LPUART3_RTS_B 0x0034 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTA13__LPI2C3_SDA 0x0034 0x01A4 0x5 0x2 -#define IMX7ULP_PAD_PTA13__TPM3_CLKIN 0x0034 0x01B0 0x6 0x1 -#define IMX7ULP_PAD_PTA13__I2S0_RXD1 0x0034 0x01E0 0x7 0x2 -#define IMX7ULP_PAD_PTA13__CMP0_OUT 0x0034 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTA13__LLWU0_P2 0x0034 0x0000 0xd 0x0 -#define IMX7ULP_PAD_PTA14__ADC1_CH8A 0x0038 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA14__PTA14 0x0038 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA14__LPSPI1_SCK 0x0038 0x012C 0x3 0x2 -#define IMX7ULP_PAD_PTA14__LPUART3_TX 0x0038 0x0224 0x4 0x2 -#define IMX7ULP_PAD_PTA14__LPI2C3_HREQ 0x0038 0x019C 0x5 0x2 -#define IMX7ULP_PAD_PTA14__TPM3_CH0 0x0038 0x0160 0x6 0x1 -#define IMX7ULP_PAD_PTA14__I2S0_MCLK 0x0038 0x01B4 0x7 0x2 -#define IMX7ULP_PAD_PTA14__LLWU0_P3 0x0038 0x0000 0xd 0x0 -#define IMX7ULP_PAD_PTA15__ADC1_CH8B 0x003C 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA15__PTA15 0x003C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA15__LPSPI1_PCS0 0x003C 0x011C 0x3 0x1 -#define IMX7ULP_PAD_PTA15__LPUART3_RX 0x003C 0x0220 0x4 0x1 -#define IMX7ULP_PAD_PTA15__TPM3_CH1 0x003C 0x0164 0x6 0x1 -#define IMX7ULP_PAD_PTA15__I2S0_TX_BCLK 0x003C 0x01C0 0x7 0x2 -#define IMX7ULP_PAD_PTA16__CMP1_IN5_3V 0x0040 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA16__PTA16 0x0040 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA16__FXIO0_D0 0x0040 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA16__LPSPI0_SOUT 0x0040 0x0118 0x3 0x2 -#define IMX7ULP_PAD_PTA16__LPUART0_CTS_B 0x0040 0x01F8 0x4 0x1 -#define IMX7ULP_PAD_PTA16__LPI2C0_SCL 0x0040 0x017C 0x5 0x1 -#define IMX7ULP_PAD_PTA16__TPM3_CH2 0x0040 0x0168 0x6 0x1 -#define IMX7ULP_PAD_PTA16__I2S0_TX_FS 0x0040 0x01C4 0x7 0x2 -#define IMX7ULP_PAD_PTA17__CMP1_IN6_3V 0x0044 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA17__PTA17 0x0044 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA17__FXIO0_D1 0x0044 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA17__LPSPI0_SCK 0x0044 0x0110 0x3 0x2 -#define IMX7ULP_PAD_PTA17__LPUART0_RTS_B 0x0044 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTA17__LPI2C0_SDA 0x0044 0x0180 0x5 0x2 -#define IMX7ULP_PAD_PTA17__TPM3_CH3 0x0044 0x016C 0x6 0x1 -#define IMX7ULP_PAD_PTA17__I2S0_TXD0 0x0044 0x0000 0x7 0x0 -#define IMX7ULP_PAD_PTA18__CMP1_IN1_3V 0x0048 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA18__PTA18 0x0048 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA18__FXIO0_D2 0x0048 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA18__LPSPI0_PCS0 0x0048 0x0100 0x3 0x2 -#define IMX7ULP_PAD_PTA18__LPUART0_TX 0x0048 0x0200 0x4 0x2 -#define IMX7ULP_PAD_PTA18__LPI2C0_HREQ 0x0048 0x0178 0x5 0x2 -#define IMX7ULP_PAD_PTA18__TPM3_CH4 0x0048 0x0170 0x6 0x1 -#define IMX7ULP_PAD_PTA18__I2S0_TXD1 0x0048 0x0000 0x7 0x0 -#define IMX7ULP_PAD_PTA18__LLWU0_P4 0x0048 0x0000 0xd 0x0 -#define IMX7ULP_PAD_PTA19__CMP1_IN3_3V 0x004C 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA19__PTA19 0x004C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA19__FXIO0_D3 0x004C 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA19__LPUART0_RX 0x004C 0x01FC 0x4 0x2 -#define IMX7ULP_PAD_PTA19__TPM3_CH5 0x004C 0x0174 0x6 0x1 -#define IMX7ULP_PAD_PTA19__I2S1_RX_BCLK 0x004C 0x01CC 0x7 0x1 -#define IMX7ULP_PAD_PTA19__LPTMR0_ALT3 0x004C 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTA19__LLWU0_P5 0x004C 0x0000 0xd 0x0 -#define IMX7ULP_PAD_PTA20__ADC0_CH10A 0x0050 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA20__PTA20 0x0050 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA20__FXIO0_D4 0x0050 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA20__LPSPI0_SIN 0x0050 0x0114 0x3 0x2 -#define IMX7ULP_PAD_PTA20__LPUART1_CTS_B 0x0050 0x0204 0x4 0x2 -#define IMX7ULP_PAD_PTA20__LPI2C1_SCL 0x0050 0x0188 0x5 0x2 -#define IMX7ULP_PAD_PTA20__TPM0_CLKIN 0x0050 0x01A8 0x6 0x1 -#define IMX7ULP_PAD_PTA20__I2S1_RX_FS 0x0050 0x01D0 0x7 0x1 -#define IMX7ULP_PAD_PTA21__ADC0_CH10B 0x0054 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA21__PTA21 0x0054 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA21__FXIO0_D5 0x0054 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA21__LPSPI0_PCS1 0x0054 0x0104 0x3 0x1 -#define IMX7ULP_PAD_PTA21__LPUART1_RTS_B 0x0054 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTA21__LPI2C1_SDA 0x0054 0x018C 0x5 0x2 -#define IMX7ULP_PAD_PTA21__TPM0_CH0 0x0054 0x0138 0x6 0x2 -#define IMX7ULP_PAD_PTA21__I2S1_RXD0 0x0054 0x01E4 0x7 0x1 -#define IMX7ULP_PAD_PTA22__ADC0_CH9A 0x0058 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA22__PTA22 0x0058 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA22__FXIO0_D6 0x0058 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA22__LPSPI0_PCS2 0x0058 0x0108 0x3 0x2 -#define IMX7ULP_PAD_PTA22__LPUART1_TX 0x0058 0x020C 0x4 0x2 -#define IMX7ULP_PAD_PTA22__LPI2C1_HREQ 0x0058 0x0184 0x5 0x2 -#define IMX7ULP_PAD_PTA22__TPM0_CH1 0x0058 0x013C 0x6 0x2 -#define IMX7ULP_PAD_PTA22__I2S1_RXD1 0x0058 0x01E8 0x7 0x1 -#define IMX7ULP_PAD_PTA22__LPTMR0_ALT2 0x0058 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTA22__EWM_OUT_B 0x0058 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTA23__ADC0_CH9B 0x005C 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA23__PTA23 0x005C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA23__FXIO0_D7 0x005C 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA23__LPSPI0_PCS3 0x005C 0x010C 0x3 0x2 -#define IMX7ULP_PAD_PTA23__LPUART1_RX 0x005C 0x0208 0x4 0x2 -#define IMX7ULP_PAD_PTA23__TPM0_CH2 0x005C 0x0140 0x6 0x2 -#define IMX7ULP_PAD_PTA23__I2S1_MCLK 0x005C 0x01C8 0x7 0x1 -#define IMX7ULP_PAD_PTA23__LLWU0_P6 0x005C 0x0000 0xd 0x0 -#define IMX7ULP_PAD_PTA24__ADC0_CH8A 0x0060 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA24__PTA24 0x0060 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA24__FXIO0_D8 0x0060 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA24__LPSPI1_PCS1 0x0060 0x0120 0x3 0x2 -#define IMX7ULP_PAD_PTA24__LPUART2_CTS_B 0x0060 0x0210 0x4 0x2 -#define IMX7ULP_PAD_PTA24__LPI2C2_SCL 0x0060 0x0194 0x5 0x2 -#define IMX7ULP_PAD_PTA24__TPM0_CH3 0x0060 0x0144 0x6 0x2 -#define IMX7ULP_PAD_PTA24__I2S1_TX_BCLK 0x0060 0x01D4 0x7 0x1 -#define IMX7ULP_PAD_PTA25__ADC0_CH8B 0x0064 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA25__PTA25 0x0064 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA25__FXIO0_D9 0x0064 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA25__LPSPI1_PCS2 0x0064 0x0124 0x3 0x2 -#define IMX7ULP_PAD_PTA25__LPUART2_RTS_B 0x0064 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTA25__LPI2C2_SDA 0x0064 0x0198 0x5 0x2 -#define IMX7ULP_PAD_PTA25__TPM0_CH4 0x0064 0x0148 0x6 0x2 -#define IMX7ULP_PAD_PTA25__I2S1_TX_FS 0x0064 0x01D8 0x7 0x1 -#define IMX7ULP_PAD_PTA26__PTA26 0x0068 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA26__JTAG_TMS_SWD_DIO 0x0068 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTA26__FXIO0_D10 0x0068 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA26__LPSPI1_PCS3 0x0068 0x0128 0x3 0x2 -#define IMX7ULP_PAD_PTA26__LPUART2_TX 0x0068 0x0218 0x4 0x2 -#define IMX7ULP_PAD_PTA26__LPI2C2_HREQ 0x0068 0x0190 0x5 0x2 -#define IMX7ULP_PAD_PTA26__TPM0_CH5 0x0068 0x014C 0x6 0x2 -#define IMX7ULP_PAD_PTA26__I2S1_RXD2 0x0068 0x01EC 0x7 0x1 -#define IMX7ULP_PAD_PTA27__PTA27 0x006C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA27__JTAG_TDO 0x006C 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTA27__FXIO0_D11 0x006C 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA27__LPUART2_RX 0x006C 0x0214 0x4 0x2 -#define IMX7ULP_PAD_PTA27__TPM1_CH1 0x006C 0x0154 0x6 0x2 -#define IMX7ULP_PAD_PTA27__I2S1_RXD3 0x006C 0x01F0 0x7 0x1 -#define IMX7ULP_PAD_PTA28__PTA28 0x0070 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA28__JTAG_TDI 0x0070 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTA28__FXIO0_D12 0x0070 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA28__LPSPI1_SIN 0x0070 0x0130 0x3 0x2 -#define IMX7ULP_PAD_PTA28__LPUART3_CTS_B 0x0070 0x021C 0x4 0x2 -#define IMX7ULP_PAD_PTA28__LPI2C3_SCL 0x0070 0x01A0 0x5 0x2 -#define IMX7ULP_PAD_PTA28__TPM1_CLKIN 0x0070 0x01AC 0x6 0x2 -#define IMX7ULP_PAD_PTA28__I2S1_TXD2 0x0070 0x0000 0x7 0x0 -#define IMX7ULP_PAD_PTA29__PTA29 0x0074 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA29__JTAG_TCLK_SWD_CLK 0x0074 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTA29__FXIO0_D13 0x0074 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA29__LPSPI1_SOUT 0x0074 0x0134 0x3 0x1 -#define IMX7ULP_PAD_PTA29__LPUART3_RTS_B 0x0074 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTA29__LPI2C3_SDA 0x0074 0x01A4 0x5 0x1 -#define IMX7ULP_PAD_PTA29__TPM1_CH0 0x0074 0x0150 0x6 0x2 -#define IMX7ULP_PAD_PTA29__I2S1_TXD3 0x0074 0x0000 0x7 0x0 -#define IMX7ULP_PAD_PTA30__ADC0_CH1A 0x0078 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA30__PTA30 0x0078 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA30__FXIO0_D14 0x0078 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA30__LPSPI1_SCK 0x0078 0x012C 0x3 0x1 -#define IMX7ULP_PAD_PTA30__LPUART3_TX 0x0078 0x0224 0x4 0x1 -#define IMX7ULP_PAD_PTA30__LPI2C3_HREQ 0x0078 0x019C 0x5 0x1 -#define IMX7ULP_PAD_PTA30__TPM2_CLKIN 0x0078 0x01F4 0x6 0x2 -#define IMX7ULP_PAD_PTA30__I2S1_TXD0 0x0078 0x0000 0x7 0x0 -#define IMX7ULP_PAD_PTA30__JTAG_TRST_B 0x0078 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTA31__ADC0_CH1B 0x007C 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTA31__PTA31 0x007C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTA31__FXIO0_D15 0x007C 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTA31__LPSPI1_PCS0 0x007C 0x011C 0x3 0x2 -#define IMX7ULP_PAD_PTA31__LPUART3_RX 0x007C 0x0220 0x4 0x2 -#define IMX7ULP_PAD_PTA31__TPM2_CH0 0x007C 0x0158 0x6 0x2 -#define IMX7ULP_PAD_PTA31__I2S1_TXD1 0x007C 0x0000 0x7 0x0 -#define IMX7ULP_PAD_PTA31__LPTMR0_ALT1 0x007C 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTA31__EWM_IN 0x007C 0x0228 0xc 0x1 -#define IMX7ULP_PAD_PTA31__LLWU0_P7 0x007C 0x0000 0xd 0x0 -#define IMX7ULP_PAD_PTB0__ADC0_CH0A 0x0080 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB0__PTB0 0x0080 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB0__FXIO0_D16 0x0080 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB0__LPSPI0_SIN 0x0080 0x0114 0x3 0x3 -#define IMX7ULP_PAD_PTB0__LPUART0_TX 0x0080 0x0200 0x4 0x3 -#define IMX7ULP_PAD_PTB0__TPM2_CH1 0x0080 0x015C 0x6 0x2 -#define IMX7ULP_PAD_PTB0__CLKOUT0 0x0080 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTB0__CMP1_OUT 0x0080 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTB0__EWM_OUT_B 0x0080 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTB1__ADC0_CH0B 0x0084 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB1__PTB1 0x0084 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB1__FXIO0_D17 0x0084 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB1__LPSPI0_SOUT 0x0084 0x0118 0x3 0x3 -#define IMX7ULP_PAD_PTB1__LPUART0_RX 0x0084 0x01FC 0x4 0x3 -#define IMX7ULP_PAD_PTB1__TPM3_CLKIN 0x0084 0x01B0 0x6 0x3 -#define IMX7ULP_PAD_PTB1__I2S1_TX_BCLK 0x0084 0x01D4 0x7 0x2 -#define IMX7ULP_PAD_PTB1__RTC_CLKOUT 0x0084 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTB1__EWM_IN 0x0084 0x0228 0xc 0x2 -#define IMX7ULP_PAD_PTB1__LLWU0_P8 0x0084 0x0000 0xd 0x0 -#define IMX7ULP_PAD_PTB2__ADC0_CH6A 0x0088 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB2__PTB2 0x0088 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB2__FXIO0_D18 0x0088 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB2__LPSPI0_SCK 0x0088 0x0110 0x3 0x3 -#define IMX7ULP_PAD_PTB2__LPUART1_TX 0x0088 0x020C 0x4 0x3 -#define IMX7ULP_PAD_PTB2__TPM3_CH0 0x0088 0x0160 0x6 0x2 -#define IMX7ULP_PAD_PTB2__I2S1_TX_FS 0x0088 0x01D8 0x7 0x2 -#define IMX7ULP_PAD_PTB2__TRACE_CLKOUT 0x0088 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTB3__ADC0_CH6B 0x008C 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB3__PTB3 0x008C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB3__FXIO0_D19 0x008C 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB3__LPSPI0_PCS0 0x008C 0x0100 0x3 0x3 -#define IMX7ULP_PAD_PTB3__LPUART1_RX 0x008C 0x0208 0x4 0x3 -#define IMX7ULP_PAD_PTB3__TPM3_CH1 0x008C 0x0164 0x6 0x2 -#define IMX7ULP_PAD_PTB3__I2S1_TXD0 0x008C 0x0000 0x7 0x0 -#define IMX7ULP_PAD_PTB3__TRACE_D0 0x008C 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTB3__LPTMR1_ALT2 0x008C 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTB3__LLWU0_P9 0x008C 0x0000 0xd 0x0 -#define IMX7ULP_PAD_PTB4__PTB4 0x0090 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB4__FXIO0_D20 0x0090 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB4__LPSPI0_PCS1 0x0090 0x0104 0x3 0x3 -#define IMX7ULP_PAD_PTB4__LPUART2_TX 0x0090 0x0218 0x4 0x3 -#define IMX7ULP_PAD_PTB4__LPI2C0_HREQ 0x0090 0x0178 0x5 0x3 -#define IMX7ULP_PAD_PTB4__TPM3_CH2 0x0090 0x0168 0x6 0x2 -#define IMX7ULP_PAD_PTB4__I2S1_TXD1 0x0090 0x0000 0x7 0x0 -#define IMX7ULP_PAD_PTB4__QSPIA_DATA7 0x0090 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTB4__TRACE_D1 0x0090 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTB4__SEC_VIO_B 0x0090 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTB5__PTB5 0x0094 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB5__FXIO0_D21 0x0094 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB5__LPSPI0_PCS2 0x0094 0x0108 0x3 0x3 -#define IMX7ULP_PAD_PTB5__LPUART2_RX 0x0094 0x0214 0x4 0x3 -#define IMX7ULP_PAD_PTB5__LPI2C1_HREQ 0x0094 0x0184 0x5 0x3 -#define IMX7ULP_PAD_PTB5__TPM3_CH3 0x0094 0x016C 0x6 0x2 -#define IMX7ULP_PAD_PTB5__I2S1_TXD2 0x0094 0x0000 0x7 0x0 -#define IMX7ULP_PAD_PTB5__QSPIA_DATA6 0x0094 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTB5__TRACE_D2 0x0094 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTB5__RTC_CLKOUT 0x0094 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTB6__ADC1_CH1A 0x0098 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB6__PTB6 0x0098 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB6__FXIO0_D22 0x0098 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB6__LPSPI0_PCS3 0x0098 0x010C 0x3 0x3 -#define IMX7ULP_PAD_PTB6__LPUART3_TX 0x0098 0x0224 0x4 0x3 -#define IMX7ULP_PAD_PTB6__LPI2C0_SCL 0x0098 0x017C 0x5 0x3 -#define IMX7ULP_PAD_PTB6__TPM3_CH4 0x0098 0x0170 0x6 0x2 -#define IMX7ULP_PAD_PTB6__I2S1_TXD3 0x0098 0x0000 0x7 0x0 -#define IMX7ULP_PAD_PTB6__QSPIA_DATA5 0x0098 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTB6__TRACE_D3 0x0098 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTB6__LPTMR1_ALT3 0x0098 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTB6__LLWU0_P10 0x0098 0x0000 0xd 0x0 -#define IMX7ULP_PAD_PTB7__ADC1_CH1B 0x009C 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB7__PTB7 0x009C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB7__FXIO0_D23 0x009C 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB7__LPSPI1_SIN 0x009C 0x0130 0x3 0x3 -#define IMX7ULP_PAD_PTB7__LPUART3_RX 0x009C 0x0220 0x4 0x3 -#define IMX7ULP_PAD_PTB7__LPI2C0_SDA 0x009C 0x0180 0x5 0x3 -#define IMX7ULP_PAD_PTB7__TPM3_CH5 0x009C 0x0174 0x6 0x2 -#define IMX7ULP_PAD_PTB7__I2S1_MCLK 0x009C 0x01C8 0x7 0x2 -#define IMX7ULP_PAD_PTB7__QSPIA_SS1_B 0x009C 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTB7__CMP1_OUT 0x009C 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTB7__LLWU0_P11 0x009C 0x0000 0xd 0x0 -#define IMX7ULP_PAD_PTB8__ADC0_CH14A_CMP0_IN0 0x00A0 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB8__PTB8 0x00A0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB8__FXIO0_D24 0x00A0 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB8__LPSPI1_SOUT 0x00A0 0x0134 0x3 0x3 -#define IMX7ULP_PAD_PTB8__LPI2C1_SCL 0x00A0 0x0188 0x5 0x3 -#define IMX7ULP_PAD_PTB8__TPM0_CLKIN 0x00A0 0x01A8 0x6 0x3 -#define IMX7ULP_PAD_PTB8__I2S1_RX_BCLK 0x00A0 0x01CC 0x7 0x2 -#define IMX7ULP_PAD_PTB8__QSPIA_SS0_B 0x00A0 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTB8__RTC_CLKOUT 0x00A0 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTB9__ADC0_CH14B_CMP0_IN2 0x00A4 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB9__PTB9 0x00A4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB9__FXIO0_D25 0x00A4 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB9__LPSPI1_SCK 0x00A4 0x012C 0x3 0x3 -#define IMX7ULP_PAD_PTB9__LPI2C1_SDA 0x00A4 0x018C 0x5 0x3 -#define IMX7ULP_PAD_PTB9__TPM0_CH0 0x00A4 0x0138 0x6 0x3 -#define IMX7ULP_PAD_PTB9__I2S1_RX_FS 0x00A4 0x01D0 0x7 0x2 -#define IMX7ULP_PAD_PTB9__QSPIA_DQS 0x00A4 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTB9__LLWU0_P12 0x00A4 0x0000 0xd 0x0 -#define IMX7ULP_PAD_PTB10__CMP0_IN1 0x00A8 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB10__PTB10 0x00A8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB10__FXIO0_D26 0x00A8 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB10__LPSPI1_PCS0 0x00A8 0x011C 0x3 0x3 -#define IMX7ULP_PAD_PTB10__LPI2C2_SCL 0x00A8 0x0194 0x5 0x3 -#define IMX7ULP_PAD_PTB10__TPM0_CH1 0x00A8 0x013C 0x6 0x3 -#define IMX7ULP_PAD_PTB10__I2S1_RXD0 0x00A8 0x01E4 0x7 0x2 -#define IMX7ULP_PAD_PTB10__TRACE_D4 0x00A8 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTB11__CMP0_IN3 0x00AC 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB11__PTB11 0x00AC 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB11__FXIO0_D27 0x00AC 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB11__LPSPI1_PCS1 0x00AC 0x0120 0x3 0x3 -#define IMX7ULP_PAD_PTB11__LPI2C2_SDA 0x00AC 0x0198 0x5 0x3 -#define IMX7ULP_PAD_PTB11__TPM1_CLKIN 0x00AC 0x01AC 0x6 0x3 -#define IMX7ULP_PAD_PTB11__I2S1_RXD1 0x00AC 0x01E8 0x7 0x2 -#define IMX7ULP_PAD_PTB11__TRACE_D5 0x00AC 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTB12__ADC1_CH13A_CMP1_IN0 0x00B0 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB12__PTB12 0x00B0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB12__FXIO0_D28 0x00B0 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB12__LPSPI1_PCS2 0x00B0 0x0124 0x3 0x3 -#define IMX7ULP_PAD_PTB12__LPUART2_TX 0x00B0 0x0218 0x4 0x4 -#define IMX7ULP_PAD_PTB12__LPI2C3_SCL 0x00B0 0x01A0 0x5 0x3 -#define IMX7ULP_PAD_PTB12__TPM1_CH0 0x00B0 0x0150 0x6 0x3 -#define IMX7ULP_PAD_PTB12__I2S1_RXD2 0x00B0 0x01EC 0x7 0x2 -#define IMX7ULP_PAD_PTB12__TRACE_D6 0x00B0 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTB13__ADC1_CH13B_CMP1_IN1 0x00B4 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB13__PTB13 0x00B4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB13__FXIO0_D29 0x00B4 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB13__LPSPI1_PCS3 0x00B4 0x0128 0x3 0x3 -#define IMX7ULP_PAD_PTB13__LPUART2_RX 0x00B4 0x0214 0x4 0x4 -#define IMX7ULP_PAD_PTB13__LPI2C3_SDA 0x00B4 0x01A4 0x5 0x3 -#define IMX7ULP_PAD_PTB13__TPM1_CH1 0x00B4 0x0154 0x6 0x3 -#define IMX7ULP_PAD_PTB13__I2S1_RXD3 0x00B4 0x01F0 0x7 0x2 -#define IMX7ULP_PAD_PTB13__QSPIA_DATA4 0x00B4 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTB13__TRACE_D7 0x00B4 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTB14__ADC1_CH2A 0x00B8 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB14__PTB14 0x00B8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB14__FXIO0_D30 0x00B8 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB14__LPI2C2_HREQ 0x00B8 0x0190 0x5 0x3 -#define IMX7ULP_PAD_PTB14__TPM2_CLKIN 0x00B8 0x01F4 0x6 0x3 -#define IMX7ULP_PAD_PTB14__QSPIA_SS1_B 0x00B8 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTB14__QSPIA_SCLK_B 0x00B8 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTB14__RTC_CLKOUT 0x00B8 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTB14__LLWU0_P13 0x00B8 0x0000 0xd 0x0 -#define IMX7ULP_PAD_PTB15__ADC1_CH2B 0x00BC 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB15__PTB15 0x00BC 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB15__FXIO0_D31 0x00BC 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTB15__LPI2C3_HREQ 0x00BC 0x019C 0x5 0x3 -#define IMX7ULP_PAD_PTB15__TPM2_CH0 0x00BC 0x0158 0x6 0x3 -#define IMX7ULP_PAD_PTB15__QSPIA_SCLK 0x00BC 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTB16__ADC0_CH4A 0x00C0 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB16__PTB16 0x00C0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB16__TPM2_CH1 0x00C0 0x015C 0x6 0x3 -#define IMX7ULP_PAD_PTB16__QSPIA_DATA3 0x00C0 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTB16__LLWU0_P14 0x00C0 0x0000 0xd 0x0 -#define IMX7ULP_PAD_PTB17__ADC0_CH4B 0x00C4 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB17__PTB17 0x00C4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB17__TPM3_CLKIN 0x00C4 0x01B0 0x6 0x2 -#define IMX7ULP_PAD_PTB17__QSPIA_DATA2 0x00C4 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTB18__ADC0_CH5A 0x00C8 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB18__PTB18 0x00C8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB18__TPM3_CH0 0x00C8 0x0160 0x6 0x3 -#define IMX7ULP_PAD_PTB18__QSPIA_DATA1 0x00C8 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTB19__ADC0_CH5B 0x00CC 0x0000 0x0 0x0 -#define IMX7ULP_PAD_PTB19__PTB19 0x00CC 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTB19__TPM3_CH1 0x00CC 0x0164 0x6 0x3 -#define IMX7ULP_PAD_PTB19__QSPIA_DATA0 0x00CC 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTB19__USB0_ID 0x00CC 0x0338 0xa 0x0 -#define IMX7ULP_PAD_PTB19__LLWU0_P15 0x00CC 0x0000 0xd 0x0 + #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027C 0x5 0x1 +#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1 #define IMX7ULP_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1 #define IMX7ULP_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024C 0x4 0x1 +#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1 #define IMX7ULP_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1 #define IMX7ULP_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1 #define IMX7ULP_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC3__PTC3 0x000C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000C 0x0248 0x4 0x1 -#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000C 0x0288 0x6 0x1 -#define IMX7ULP_PAD_PTC3__FB_AD3 0x000C 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1 +#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1 +#define IMX7ULP_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0 #define IMX7ULP_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1 -#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02A0 0x3 0x1 +#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1 #define IMX7ULP_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1 -#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02BC 0x5 0x1 -#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028C 0x6 0x1 +#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1 +#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1 #define IMX7ULP_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1 -#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02A4 0x3 0x1 +#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1 #define IMX7ULP_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02C0 0x5 0x1 +#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1 #define IMX7ULP_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1 #define IMX7ULP_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020C 0x2 0x1 -#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02A8 0x3 0x1 +#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1 +#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1 #define IMX7ULP_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1 -#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02B8 0x5 0x1 +#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1 #define IMX7ULP_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1 #define IMX7ULP_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC7__PTC7 0x001C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001C 0x0210 0x2 0x1 -#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001C 0x0254 0x4 0x1 -#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001C 0x02C8 0x6 0x1 -#define IMX7ULP_PAD_PTC7__FB_AD7 0x001C 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1 +#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1 +#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1 +#define IMX7ULP_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0 #define IMX7ULP_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1 -#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02B0 0x3 0x1 -#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025C 0x4 0x1 -#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02FC 0x5 0x1 -#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02CC 0x6 0x1 +#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1 +#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1 +#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1 +#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1 #define IMX7ULP_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1 -#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02B4 0x3 0x1 +#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1 #define IMX7ULP_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0 #define IMX7ULP_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1 -#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02C4 0x6 0x1 +#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1 #define IMX7ULP_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021C 0x2 0x1 -#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02AC 0x3 0x1 +#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1 +#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1 #define IMX7ULP_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1 -#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02F8 0x5 0x1 -#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02E8 0x6 0x1 +#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1 +#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1 #define IMX7ULP_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC11__PTC11 0x002C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002C 0x0220 0x2 0x1 -#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002C 0x029C 0x3 0x1 -#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002C 0x0260 0x4 0x1 -#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002C 0x02EC 0x6 0x1 -#define IMX7ULP_PAD_PTC11__FB_AD11 0x002C 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1 +#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1 +#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1 +#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1 +#define IMX7ULP_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0 #define IMX7ULP_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1 #define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 #define IMX7ULP_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1 #define IMX7ULP_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1 -#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02F0 0x6 0x1 +#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1 #define IMX7ULP_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1 #define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 #define IMX7ULP_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030C 0x5 0x1 -#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02F4 0x6 0x1 +#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1 +#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1 #define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC13__USB0_ID 0x0034 0x0338 0xb 0x1 #define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022C 0x2 0x1 -#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031C 0x3 0x1 +#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1 +#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1 #define IMX7ULP_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1 #define IMX7ULP_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1 -#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02DC 0x6 0x1 +#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1 #define IMX7ULP_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTC15__PTC15 0x003C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003C 0x0230 0x2 0x1 -#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003C 0x026C 0x4 0x1 -#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003C 0x02E0 0x6 0x1 -#define IMX7ULP_PAD_PTC15__FB_AD15 0x003C 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003C 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1 +#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1 +#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1 +#define IMX7ULP_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0 #define IMX7ULP_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1 #define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1 -#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02E4 0x6 0x1 +#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1 #define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTC16__USB1_OC2 0x0040 0x0334 0xb 0x1 #define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0 #define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1 #define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1 -#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02D8 0x6 0x1 +#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1 #define IMX7ULP_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0 #define IMX7ULP_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023C 0x2 0x1 +#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1 #define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1 -#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02D0 0x6 0x1 +#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1 #define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0 #define IMX7ULP_PAD_PTC18__USB0_ID 0x0048 0x0338 0xb 0x2 -#define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033C 0xc 0x1 -#define IMX7ULP_PAD_PTC19__PTC19 0x004C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004C 0x0240 0x2 0x1 -#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004C 0x0310 0x3 0x1 -#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004C 0x02D4 0x6 0x1 -#define IMX7ULP_PAD_PTC19__FB_A16 0x004C 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTC19__USB0_ID 0x004C 0x0338 0xa 0x3 -#define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004C 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTC19__VIU_DE 0x004C 0x033C 0xc 0x3 +#define IMX7ULP_PAD_PTC18__VIU_DE 0x0048 0x033c 0xc 0x1 +#define IMX7ULP_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1 +#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1 +#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1 +#define IMX7ULP_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTC19__USB0_ID 0x004c 0x0338 0xa 0x3 +#define IMX7ULP_PAD_PTC19__USB1_PWR2 0x004c 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTC19__VIU_DE 0x004c 0x033c 0xc 0x3 #define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0 #define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0 #define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0 #define IMX7ULP_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0 #define IMX7ULP_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0 #define IMX7ULP_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD3__PTD3 0x008C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008C 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0 #define IMX7ULP_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0 #define IMX7ULP_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0 #define IMX7ULP_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0 #define IMX7ULP_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0 #define IMX7ULP_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0 #define IMX7ULP_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD7__PTD7 0x009C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009C 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD8__PTD8 0x00A0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00A0 0x0298 0x6 0x2 -#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00A0 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD9__PTD9 0x00A4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00A4 0x0280 0x6 0x2 -#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00A4 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD10__PTD10 0x00A8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00A8 0x0284 0x6 0x2 -#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00A8 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTD11__PTD11 0x00AC 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00AC 0x0288 0x6 0x2 -#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00AC 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2 +#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2 +#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2 +#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2 +#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0 #define IMX7ULP_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0 #define IMX7ULP_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02A0 0x3 0x2 +#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2 #define IMX7ULP_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2 #define IMX7ULP_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2 #define IMX7ULP_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0 #define IMX7ULP_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0 #define IMX7ULP_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0 #define IMX7ULP_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02A4 0x3 0x2 +#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2 #define IMX7ULP_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027C 0x5 0x2 +#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2 #define IMX7ULP_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0 #define IMX7ULP_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0 #define IMX7ULP_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0 #define IMX7ULP_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02A8 0x3 0x2 -#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024C 0x4 0x2 +#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2 +#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2 #define IMX7ULP_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2 #define IMX7ULP_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE3__PTE3 0x010C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010C 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010C 0x0248 0x4 0x2 -#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010C 0x02C8 0x6 0x2 -#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010C 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2 +#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2 +#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0 #define IMX7ULP_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0 #define IMX7ULP_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02B0 0x3 0x2 +#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2 #define IMX7ULP_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2 -#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02BC 0x5 0x2 -#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02CC 0x6 0x2 +#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2 +#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2 #define IMX7ULP_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0 #define IMX7ULP_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0 #define IMX7ULP_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02B4 0x3 0x2 +#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2 #define IMX7ULP_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02C0 0x5 0x2 -#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02C4 0x6 0x2 +#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2 +#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2 #define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033C 0xc 0x2 +#define IMX7ULP_PAD_PTE5__VIU_DE 0x0114 0x033c 0xc 0x2 #define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0 #define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02AC 0x3 0x2 +#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2 #define IMX7ULP_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2 -#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02B8 0x5 0x2 -#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02E8 0x6 0x2 +#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2 +#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2 #define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0 #define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0 #define IMX7ULP_PAD_PTE6__USB0_OC 0x0118 0x0330 0xb 0x1 -#define IMX7ULP_PAD_PTE7__PTE7 0x011C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011C 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011C 0x029C 0x3 0x2 -#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011C 0x0254 0x4 0x2 -#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011C 0x02EC 0x6 0x2 -#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011C 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE7__FB_A18 0x011C 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011C 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE7__USB0_PWR 0x011C 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTE7__VIU_FID 0x011C 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE7__USB0_PWR 0x011c 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2 +#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2 +#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2 +#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0 #define IMX7ULP_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0 #define IMX7ULP_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0 #define IMX7ULP_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0 #define IMX7ULP_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2 -#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025C 0x4 0x2 -#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02FC 0x5 0x2 -#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02F0 0x6 0x2 +#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2 +#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2 +#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2 #define IMX7ULP_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1 #define IMX7ULP_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0 #define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0 @@ -673,220 +259,220 @@ #define IMX7ULP_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2 #define IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0 #define IMX7ULP_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2 -#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02F4 0x6 0x2 -#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032C 0x7 0x1 +#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2 +#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1 #define IMX7ULP_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0 #define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0 #define IMX7ULP_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0 #define IMX7ULP_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0 #define IMX7ULP_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0 #define IMX7ULP_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031C 0x3 0x2 +#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2 #define IMX7ULP_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2 -#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02F8 0x5 0x2 -#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02DC 0x6 0x2 +#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2 +#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2 #define IMX7ULP_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0 #define IMX7ULP_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0 #define IMX7ULP_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE11__PTE11 0x012C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012C 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE11__VIU_D19 0x012C 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012C 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012C 0x0260 0x4 0x2 -#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012C 0x02E0 0x6 0x2 -#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012C 0x0000 0x8 0x0 -#define IMX7ULP_PAD_PTE11__FB_A20 0x012C 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2 +#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2 +#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0 +#define IMX7ULP_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0 #define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2 +#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 #define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0 #define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2 #define IMX7ULP_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2 #define IMX7ULP_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2 -#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02E4 0x6 0x2 +#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2 #define IMX7ULP_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2 #define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE12__USB1_OC2 0x0130 0x0334 0xb 0x2 -#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0 #define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 #define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0 #define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2 #define IMX7ULP_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030C 0x5 0x2 -#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02D8 0x6 0x2 -#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032C 0x8 0x2 +#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2 +#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2 +#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2 #define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE13__USB1_PWR2 0x0134 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0 #define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2 +#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 #define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0 #define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2 #define IMX7ULP_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2 #define IMX7ULP_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2 -#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02D0 0x6 0x2 +#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2 #define IMX7ULP_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0 #define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE14__USB0_OC 0x0138 0x0330 0xb 0x2 -#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTE15__PTE15 0x013C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013C 0x0000 0x2 0x0 -#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013C 0x0310 0x3 0x2 -#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013C 0x026C 0x4 0x2 -#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013C 0x02D4 0x6 0x2 -#define IMX7ULP_PAD_PTE15__FB_A24 0x013C 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013C 0x0000 0xa 0x0 -#define IMX7ULP_PAD_PTE15__USB0_PWR 0x013C 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTE15__VIU_D23 0x013C 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0 +#define IMX7ULP_PAD_PTE15__USB0_PWR 0x013c 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0 +#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2 +#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2 +#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2 +#define IMX7ULP_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0 #define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033c 0xc 0x0 #define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3 #define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3 #define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3 #define IMX7ULP_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x033C 0xc 0x0 #define IMX7ULP_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 #define IMX7ULP_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027C 0x5 0x3 +#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3 #define IMX7ULP_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3 #define IMX7ULP_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0 #define IMX7ULP_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024C 0x4 0x3 +#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3 #define IMX7ULP_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3 #define IMX7ULP_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3 #define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF3__PTF3 0x018C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018C 0x0248 0x4 0x3 -#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018C 0x0288 0x6 0x3 -#define IMX7ULP_PAD_PTF3__FB_AD16 0x018C 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018C 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3 +#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3 +#define IMX7ULP_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0 #define IMX7ULP_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 #define IMX7ULP_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2 -#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02A0 0x3 0x3 +#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3 #define IMX7ULP_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3 -#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02BC 0x5 0x3 -#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028C 0x6 0x2 +#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3 +#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2 #define IMX7ULP_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0 #define IMX7ULP_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 #define IMX7ULP_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2 -#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02A4 0x3 0x3 +#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3 #define IMX7ULP_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02C0 0x5 0x3 +#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3 #define IMX7ULP_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2 #define IMX7ULP_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0 #define IMX7ULP_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020C 0x2 0x2 -#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02A8 0x3 0x3 +#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2 +#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3 #define IMX7ULP_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3 -#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02B8 0x5 0x3 +#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3 #define IMX7ULP_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2 #define IMX7ULP_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF7__PTF7 0x019C 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019C 0x0210 0x2 0x2 -#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019C 0x0254 0x4 0x3 -#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019C 0x02C8 0x6 0x3 -#define IMX7ULP_PAD_PTF7__FB_AD20 0x019C 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF7__VIU_D3 0x019C 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF8__PTF8 0x01A0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01A0 0x0214 0x2 0x2 -#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01A0 0x02B0 0x3 0x3 -#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01A0 0x025C 0x4 0x3 -#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01A0 0x02FC 0x5 0x3 -#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01A0 0x02CC 0x6 0x3 -#define IMX7ULP_PAD_PTF8__FB_AD21 0x01A0 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF8__USB1_CLK 0x01A0 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF8__VIU_D4 0x01A0 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF9__PTF9 0x01A4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01A4 0x0218 0x2 0x2 -#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01A4 0x02B4 0x3 0x3 -#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01A4 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01A4 0x0300 0x5 0x3 -#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01A4 0x02C4 0x6 0x3 -#define IMX7ULP_PAD_PTF9__FB_AD22 0x01A4 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF9__USB1_NXT 0x01A4 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF9__VIU_D5 0x01A4 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF10__PTF10 0x01A8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01A8 0x021C 0x2 0x2 -#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01A8 0x02AC 0x3 0x3 -#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01A8 0x0264 0x4 0x3 -#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01A8 0x02F8 0x5 0x3 -#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01A8 0x02E8 0x6 0x3 -#define IMX7ULP_PAD_PTF10__FB_AD23 0x01A8 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF10__USB1_STP 0x01A8 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF10__VIU_D6 0x01A8 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF11__PTF11 0x01AC 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01AC 0x0220 0x2 0x2 -#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01AC 0x029C 0x3 0x3 -#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01AC 0x0260 0x4 0x3 -#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01AC 0x02EC 0x6 0x3 -#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01AC 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF11__USB1_DIR 0x01AC 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF11__VIU_D7 0x01AC 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF12__PTF12 0x01B0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01B0 0x0224 0x2 0x2 -#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01B0 0x0314 0x3 0x3 -#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01B0 0x0268 0x4 0x3 -#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01B0 0x0308 0x5 0x3 -#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01B0 0x02F0 0x6 0x3 -#define IMX7ULP_PAD_PTF12__FB_AD24 0x01B0 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF12__USB1_DATA0 0x01B0 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF12__VIU_D8 0x01B0 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF13__PTF13 0x01B4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01B4 0x0228 0x2 0x2 -#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01B4 0x0318 0x3 0x3 -#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01B4 0x0000 0x4 0x0 -#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01B4 0x030C 0x5 0x3 -#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01B4 0x02F4 0x6 0x3 -#define IMX7ULP_PAD_PTF13__FB_AD25 0x01B4 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF13__USB1_DATA1 0x01B4 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF13__VIU_D9 0x01B4 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF14__PTF14 0x01B8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01B8 0x022C 0x2 0x2 -#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01B8 0x031C 0x3 0x3 -#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01B8 0x0270 0x4 0x3 -#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01B8 0x0304 0x5 0x3 -#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01B8 0x02DC 0x6 0x3 -#define IMX7ULP_PAD_PTF14__FB_AD26 0x01B8 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF14__USB1_DATA2 0x01B8 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF14__VIU_D10 0x01B8 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF15__PTF15 0x01BC 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01BC 0x0230 0x2 0x2 -#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01BC 0x026C 0x4 0x3 -#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01BC 0x02E0 0x6 0x3 -#define IMX7ULP_PAD_PTF15__FB_AD27 0x01BC 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF15__USB1_DATA3 0x01BC 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF15__VIU_D11 0x01BC 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF16__PTF16 0x01C0 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF16__USB1_DATA4 0x01C0 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF16__VIU_D12 0x01C0 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01C0 0x0234 0x2 0x2 -#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01C0 0x0324 0x3 0x3 -#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01C0 0x02E4 0x6 0x3 -#define IMX7ULP_PAD_PTF16__FB_AD28 0x01C0 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF17__PTF17 0x01C4 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF17__USB1_DATA5 0x01C4 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF17__VIU_D13 0x01C4 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01C4 0x0238 0x2 0x2 -#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01C4 0x0328 0x3 0x3 -#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01C4 0x02D8 0x6 0x3 -#define IMX7ULP_PAD_PTF17__FB_AD29 0x01C4 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF18__PTF18 0x01C8 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF18__USB1_DATA6 0x01C8 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF18__VIU_D14 0x01C8 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01C8 0x023C 0x2 0x2 -#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01C8 0x0320 0x3 0x3 -#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01C8 0x02D0 0x6 0x3 -#define IMX7ULP_PAD_PTF18__FB_AD30 0x01C8 0x0000 0x9 0x0 -#define IMX7ULP_PAD_PTF19__PTF19 0x01CC 0x0000 0x1 0x0 -#define IMX7ULP_PAD_PTF19__USB1_DATA7 0x01CC 0x0000 0xb 0x0 -#define IMX7ULP_PAD_PTF19__VIU_D15 0x01CC 0x0000 0xc 0x0 -#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01CC 0x0240 0x2 0x2 -#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01CC 0x0310 0x3 0x3 -#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01CC 0x02D4 0x6 0x3 -#define IMX7ULP_PAD_PTF19__FB_AD31 0x01CC 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2 +#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3 +#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3 +#define IMX7ULP_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2 +#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3 +#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3 +#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3 +#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3 +#define IMX7ULP_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2 +#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3 +#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3 +#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3 +#define IMX7ULP_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2 +#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3 +#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3 +#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3 +#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3 +#define IMX7ULP_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2 +#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3 +#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3 +#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3 +#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2 +#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3 +#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3 +#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3 +#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3 +#define IMX7ULP_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2 +#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3 +#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0 +#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3 +#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3 +#define IMX7ULP_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2 +#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3 +#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3 +#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3 +#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3 +#define IMX7ULP_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2 +#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3 +#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3 +#define IMX7ULP_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2 +#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3 +#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3 +#define IMX7ULP_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2 +#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3 +#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3 +#define IMX7ULP_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2 +#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3 +#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3 +#define IMX7ULP_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0 +#define IMX7ULP_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0 +#define IMX7ULP_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0 +#define IMX7ULP_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0 +#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2 +#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3 +#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3 +#define IMX7ULP_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0

#endif /* __DTS_IMX7ULP_PINFUNC_H */ diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi index 494b9d98b2..bcec98b964 100644 --- a/arch/arm/dts/imx7ulp.dtsi +++ b/arch/arm/dts/imx7ulp.dtsi @@ -1,28 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2021 NXP - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * Dong Aisheng aisheng.dong@nxp.com */

#include <dt-bindings/clock/imx7ulp-clock.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/gpio.h> -#include "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> + #include "imx7ulp-pinfunc.h"

/ { interrupt-parent = <&intc>;

+ #address-cells = <1>; + #size-cells = <1>; + aliases { - gpio0 = &gpio4; - gpio1 = &gpio5; - gpio2 = &gpio0; - gpio3 = &gpio1; - gpio4 = &gpio2; - gpio5 = &gpio3; + gpio0 = &gpio_ptc; + gpio1 = &gpio_ptd; + gpio2 = &gpio_pte; + gpio3 = &gpio_ptf; + i2c0 = &lpi2c6; + i2c1 = &lpi2c7; mmc0 = &usdhc0; mmc1 = &usdhc1; serial0 = &lpuart4; @@ -30,44 +31,17 @@ serial2 = &lpuart6; serial3 = &lpuart7; usbphy0 = &usbphy1; - usb0 = &usbotg1; - i2c4 = &lpi2c4; - i2c5 = &lpi2c5; - i2c6 = &lpi2c6; - i2c7 = &lpi2c7; - spi0 = &qspi1; };

cpus { #address-cells = <1>; #size-cells = <0>;

- cpu0: cpu@0 { + cpu0: cpu@f00 { compatible = "arm,cortex-a7"; device_type = "cpu"; - reg = <0>; - }; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - /* global autoconfigured region for contiguous allocations */ - linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0xC000000>; - alignment = <0x2000>; - linux,cma-default; - }; - - rpmsg_reserved: rpmsg@9FFF0000 { - no-map; - reg = <0x9FF00000 0x100000>; + reg = <0xf00>; }; - };

intc: interrupt-controller@40021000 { @@ -75,128 +49,77 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x40021000 0x1000>, - <0x40022000 0x100>; + <0x40022000 0x1000>; };

- clocks { - #address-cells = <1>; - #size-cells = <0>; - - ckil: clock@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc: clock@1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; - - sirc: clock@2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - clock-output-names = "sirc"; - }; + rosc: clock-rosc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "rosc"; + #clock-cells = <0>; + };

- firc: clock@3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - clock-output-names = "firc"; - }; + sosc: clock-sosc { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "sosc"; + #clock-cells = <0>; + };

- upll: clock@4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <480000000>; - clock-output-names = "upll"; - }; + sirc: clock-sirc { + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-output-names = "sirc"; + #clock-cells = <0>; + };

- mpll: clock@5 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <480000000>; - clock-output-names = "mpll"; - }; + firc: clock-firc { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + clock-output-names = "firc"; + #clock-cells = <0>; };

- sram: sram@20000000 { - compatible = "fsl,lpm-sram"; - reg = <0x1fffc000 0x4000>; + upll: clock-upll { + compatible = "fixed-clock"; + clock-frequency = <480000000>; + clock-output-names = "upll"; + #clock-cells = <0>; };

- ahbbridge0: ahb-bridge0@40000000 { - compatible = "fsl,aips-bus", "simple-bus"; + ahbbridge0: bus@40000000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x40000000 0x800000>; ranges;

- edma0: dma-controller@40080000 { + edma1: dma-controller@40080000 { #dma-cells = <2>; - compatible = "nxp,imx7ulp-edma"; + compatible = "fsl,imx7ulp-edma"; reg = <0x40080000 0x2000>, <0x40210000 0x1000>; dma-channels = <32>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clock-names = "dma", "dmamux0"; - clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>; - }; - - mu: mu@40220000 { - compatible = "fsl,imx7ulp-mu", "fsl,imx6sx-mu"; - reg = <0x40220000 0x1000>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; - }; - - nmi: nmi@40220000 { - compatible = "fsl,imx7ulp-nmi"; - reg = <0x40220000 0x1000>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - status = "okay"; - }; - - rpmsg: rpmsg{ - compatible = "fsl,imx7ulp-rpmsg"; - memory-region = <&rpmsg_reserved>; - status = "disabled"; - }; - - snvs: snvs@40230000 { - compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; - reg = <0x40230000 0x10000>; - - snvs_rtc: snvs-rtc-lp{ - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap =<&snvs>; - offset = <0x34>; - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "snvs-rtc"; - clocks = <&clks IMX7ULP_CLK_SNVS>; - }; + clocks = <&pcc2 IMX7ULP_CLK_DMA1>, + <&pcc2 IMX7ULP_CLK_DMA_MUX1>; };

crypto: crypto@40240000 { @@ -205,8 +128,8 @@ #size-cells = <1>; reg = <0x40240000 0x10000>; ranges = <0 0x40240000 0x10000>; - clocks = <&clks IMX7ULP_CLK_CAAM>, - <&clks IMX7ULP_CLK_NIC1_BUS_DIV>; + clocks = <&pcc2 IMX7ULP_CLK_CAAM>, + <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>; clock-names = "aclk", "ipg";

sec_jr0: jr@1000 { @@ -222,105 +145,55 @@ }; };

- tpm5: tpm@40260000 { - compatible = "fsl,imx7ulp-tpm"; - reg = <0x40260000 0x1000>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_LPTPM5>; - }; - - lpit: 1@40270000 { - compatible = "fsl,imx-lpit"; - reg = <0x40270000 0x1000>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - /* clocks = <&lpclk>;*/ - clocks = <&clks IMX7ULP_CLK_LPIT1>; - assigned-clock-rates = <48000000>; - assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; - }; - - lpi2c4: lpi2c4@402B0000 { - compatible = "fsl,imx7ulp-lpi2c"; - reg = <0x402B0000 0x10000>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_LPI2C4>; - clock-names = "ipg"; - assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - lpi2c5: lpi2c4@402C0000 { - compatible = "fsl,imx7ulp-lpi2c"; - reg = <0x402C0000 0x10000>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_LPI2C5>; - clock-names = "ipg"; - assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - lpspi2: lpspi@40290000 { - compatible = "fsl,imx7ulp-spi"; - reg = <0x40290000 0x10000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_LPSPI2>; - clock-names = "ipg"; - assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - lpspi3: lpspi@402A0000 { - compatible = "fsl,imx7ulp-spi"; - reg = <0x402A0000 0x10000>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_LPSPI3>; - clock-names = "ipg"; - assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <48000000>; - status = "disabled"; - }; - - lpuart4: serial@402D0000 { + lpuart4: serial@402d0000 { compatible = "fsl,imx7ulp-lpuart"; - reg = <0x402D0000 0x1000>; + reg = <0x402d0000 0x1000>; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_LPUART4>; + clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; clock-names = "ipg"; - assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>; - assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; assigned-clock-rates = <24000000>; status = "disabled"; };

- lpuart5: serial@402E0000 { + lpuart5: serial@402e0000 { compatible = "fsl,imx7ulp-lpuart"; - reg = <0x402E0000 0x1000>; + reg = <0x402e0000 0x1000>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_LPUART5>; + clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; clock-names = "ipg"; - assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; assigned-clock-rates = <48000000>; - dmas = <&edma0 0 20>, <&edma0 0 19>; - dma-names = "tx","rx"; status = "disabled"; };

+ tpm4: pwm@40250000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x40250000 0x1000>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm5: tpm@40260000 { + compatible = "fsl,imx7ulp-tpm"; + reg = <0x40260000 0x1000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&pcc2 IMX7ULP_CLK_LPTPM5>; + clock-names = "ipg", "per"; + }; + usbotg1: usb@40330000 { - compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", - "fsl,imx27-usb"; + compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; reg = <0x40330000 0x200>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_USB0>; - fsl,usbphy = <&usbphy1>; + clocks = <&pcc2 IMX7ULP_CLK_USB0>; + phys = <&usbphy1>; fsl,usbmisc = <&usbmisc1 0>; ahb-burst-config = <0x0>; tx-burst-size-dword = <0x8>; @@ -329,314 +202,260 @@ };

usbmisc1: usbmisc@40330200 { + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc"; #index-cells = <1>; - compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", - "fsl,imx6q-usbmisc"; reg = <0x40330200 0x200>; };

- usbphy1: usbphy@0x40350000 { - compatible = "fsl,imx7ulp-usbphy", - "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + usbphy1: usb-phy@40350000 { + compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy"; reg = <0x40350000 0x1000>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_USB_PHY>; - nxp,sim = <&sim>; + clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>; + #phy-cells = <0>; };

- usdhc0: usdhc@40370000 { - compatible = "fsl,imx7ulp-usdhc"; + usdhc0: mmc@40370000 { + compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; reg = <0x40370000 0x10000>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, - <&clks IMX7ULP_CLK_NIC1_DIV>, - <&clks IMX7ULP_CLK_USDHC0>; - clock-names ="ipg", "ahb", "per"; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&pcc2 IMX7ULP_CLK_USDHC0>; + clock-names = "ipg", "ahb", "per"; bus-width = <4>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; status = "disabled"; };

- usdhc1: usdhc@40380000 { - compatible = "fsl,imx7ulp-usdhc"; + usdhc1: mmc@40380000 { + compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc"; reg = <0x40380000 0x10000>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, - <&clks IMX7ULP_CLK_NIC1_DIV>, - <&clks IMX7ULP_CLK_USDHC1>; - clock-names ="ipg", "ahb", "per"; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&pcc2 IMX7ULP_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; bus-width = <4>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; status = "disabled"; };

- wdog1: wdog@403D0000 { - compatible = "fsl,imx7ulp-wdt"; - reg = <0x403D0000 0x10000>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_WDG1>; - assigned-clocks = <&clks IMX7ULP_CLK_WDG1>; - assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>; - /* - * As the 1KHz LPO clock rate is not trimed,the actually clock - * is about 667Hz, so the init timeout 60s should set 40*1000 - * in the TOVAL register. - */ - timeout-sec = <40>; + scg1: clock-controller@403e0000 { + compatible = "fsl,imx7ulp-scg1"; + reg = <0x403e0000 0x10000>; + clocks = <&rosc>, <&sosc>, <&sirc>, + <&firc>, <&upll>; + clock-names = "rosc", "sosc", "sirc", + "firc", "upll"; + #clock-cells = <1>; };

- wdog2: wdog@40430000 { + wdog1: watchdog@403d0000 { compatible = "fsl,imx7ulp-wdt"; - reg = <0x40430000 0x10000>; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_WDG2>; - assigned-clocks = <&clks IMX7ULP_CLK_WDG2>; - assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>; + reg = <0x403d0000 0x10000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc2 IMX7ULP_CLK_WDG1>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; timeout-sec = <40>; };

- clks: scg1@403E0000 { - compatible = "fsl,imx7ulp-scg1"; - reg = <0x403E0000 0x10000>; - clocks = <&ckil>, <&osc>, <&sirc>, - <&firc>, <&upll>, <&mpll>; - clock-names = "ckil", "osc", "sirc", - "firc", "upll", "mpll"; + pcc2: clock-controller@403f0000 { + compatible = "fsl,imx7ulp-pcc2"; + reg = <0x403f0000 0x10000>; #clock-cells = <1>; - assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>, - <&clks IMX7ULP_CLK_USDHC1>; - assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>, - <&clks IMX7ULP_CLK_NIC1_DIV>; - }; - - pcc2: pcc2@403F0000 { - compatible = "fsl,imx7ulp-pcc2"; - reg = <0x403F0000 0x10000>; - }; - - pmc1: pmc1@40400000 { - compatible = "fsl,imx7ulp-pmc1"; - reg = <0x40400000 0x1000>; - }; - - smc1: smc1@40410000 { + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&scg1 IMX7ULP_CLK_DDR_DIV>, + <&scg1 IMX7ULP_CLK_APLL_PFD2>, + <&scg1 IMX7ULP_CLK_APLL_PFD1>, + <&scg1 IMX7ULP_CLK_APLL_PFD0>, + <&scg1 IMX7ULP_CLK_UPLL>, + <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_ROSC>, + <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; + clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", + "apll_pfd2", "apll_pfd1", "apll_pfd0", + "upll", "sosc_bus_clk", + "firc_bus_clk", "rosc", "spll_bus_clk"; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + }; + + smc1: clock-controller@40410000 { compatible = "fsl,imx7ulp-smc1"; reg = <0x40410000 0x1000>; + #clock-cells = <1>; + clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>, + <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>; + clock-names = "divcore", "hsrun_divcore"; };

+ pcc3: clock-controller@40b30000 { + compatible = "fsl,imx7ulp-pcc3"; + reg = <0x40b30000 0x10000>; + #clock-cells = <1>; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&scg1 IMX7ULP_CLK_NIC1_DIV>, + <&scg1 IMX7ULP_CLK_DDR_DIV>, + <&scg1 IMX7ULP_CLK_APLL_PFD2>, + <&scg1 IMX7ULP_CLK_APLL_PFD1>, + <&scg1 IMX7ULP_CLK_APLL_PFD0>, + <&scg1 IMX7ULP_CLK_UPLL>, + <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, + <&scg1 IMX7ULP_CLK_ROSC>, + <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; + clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", + "apll_pfd2", "apll_pfd1", "apll_pfd0", + "upll", "sosc_bus_clk", + "firc_bus_clk", "rosc", "spll_bus_clk"; + }; };

- ahbbridge1: ahb-bridge1@40800000 { - compatible = "fsl,aips-bus", "simple-bus"; + ahbbridge1: bus@40800000 { + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x40800000 0x800000>; ranges;

- lpi2c6: lpi2c6@40A40000 { + lpi2c6: i2c@40a40000 { compatible = "fsl,imx7ulp-lpi2c"; - reg = <0x40A40000 0x10000>; + reg = <0x40a40000 0x10000>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_LPI2C6>; + clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; clock-names = "ipg"; - assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; assigned-clock-rates = <48000000>; status = "disabled"; };

- lpi2c7: lpi2c7@40A50000 { + lpi2c7: i2c@40a50000 { compatible = "fsl,imx7ulp-lpi2c"; - reg = <0x40A50000 0x10000>; + reg = <0x40a50000 0x10000>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_LPI2C7>; + clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; clock-names = "ipg"; - assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; assigned-clock-rates = <48000000>; status = "disabled"; };

- lpuart6: serial@40A60000 { + lpuart6: serial@40a60000 { compatible = "fsl,imx7ulp-lpuart"; - reg = <0x40A60000 0x1000>; + reg = <0x40a60000 0x1000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_LPUART6>; + clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; clock-names = "ipg"; - assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; assigned-clock-rates = <48000000>; - dmas = <&edma0 0 22>, <&edma0 0 21>; - dma-names = "tx","rx"; status = "disabled"; };

- lpuart7: serial@40A70000 { + lpuart7: serial@40a70000 { compatible = "fsl,imx7ulp-lpuart"; - reg = <0x40A70000 0x1000>; + reg = <0x40a70000 0x1000>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_LPUART7>; + clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; clock-names = "ipg"; - assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>; - assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; - assigned-clock-rates = <50000000>; - dmas = <&edma0 0 24>, <&edma0 0 23>; - dma-names = "tx","rx"; - status = "disabled"; - }; - - lcdif: lcdif@40AA0000 { - compatible = "fsl,imx7ulp-lcdif"; - reg = <0x40aa0000 0x10000>; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_DUMMY>, - <&clks IMX7ULP_CLK_LCDIF>, - <&clks IMX7ULP_CLK_DUMMY>; - clock-names = "axi", "pix", "disp_axi"; - status = "disabled"; - }; - - mipi_dsi: mipi_dsi@40A90000 { - compatible = "fsl,imx7ulp-mipi-dsi"; - reg = <0x40A90000 0x10000>; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_DSI>; - clock-names = "mipi_dsi_clk"; - sim = <&sim>; + assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-rates = <48000000>; status = "disabled"; };

- mmdc: mmdc@40ab0000 { - compatible = "fsl,imx7ulp-mmdc"; - reg = <0x40ab0000 0x4000>; + memory-controller@40ab0000 { + compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; + reg = <0x40ab0000 0x1000>; + clocks = <&pcc3 IMX7ULP_CLK_MMDC>; };

- pcc3: pcc3@40B30000 { - compatible = "fsl,imx7ulp-pcc3"; - reg = <0x40B30000 0x10000>; - }; - - iomuxc: iomuxc@4103D000 { - compatible = "fsl,imx7ulp-iomuxc-0"; - reg = <0x4103D000 0x1000>; - fsl,mux_mask = <0xf00>; - status = "disabled"; - }; - - iomuxc1: iomuxc1@40ac0000 { - compatible = "fsl,imx7ulp-iomuxc-1"; + iomuxc1: pinctrl@40ac0000 { + compatible = "fsl,imx7ulp-iomuxc1"; reg = <0x40ac0000 0x1000>; - fsl,mux_mask = <0xf00>; };

- gpio4: gpio@4103f000 { - compatible = "fsl,imx7ulp-gpio"; - reg = <0x4103f000 0x1000 0x4100F000 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&iomuxc 0 0 32>; - }; - - gpio5: gpio@41040000 { - compatible = "fsl,imx7ulp-gpio"; - reg = <0x41040000 0x1000 0x4100F040 0x40>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&iomuxc 0 32 32>; - }; - - gpio0: gpio@40ae0000 { - compatible = "fsl,imx7ulp-gpio"; - reg = <0x40ae0000 0x1000 0x400F0000 0x40>; + gpio_ptc: gpio@40ae0000 { + compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; + reg = <0x40ae0000 0x1000 0x400f0000 0x40>; gpio-controller; #gpio-cells = <2>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc1 0 0 32>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLC>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 0 20>; };

- gpio1: gpio@40af0000 { - compatible = "fsl,imx7ulp-gpio"; - reg = <0x40af0000 0x1000 0x400F0040 0x40>; + gpio_ptd: gpio@40af0000 { + compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; + reg = <0x40af0000 0x1000 0x400f0040 0x40>; gpio-controller; #gpio-cells = <2>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc1 0 32 32>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLD>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 32 12>; };

- gpio2: gpio@40b00000 { - compatible = "fsl,imx7ulp-gpio"; - reg = <0x40b00000 0x1000 0x400F0080 0x40>; + gpio_pte: gpio@40b00000 { + compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; + reg = <0x40b00000 0x1000 0x400f0080 0x40>; gpio-controller; #gpio-cells = <2>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc1 0 64 32>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLE>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 64 16>; };

- gpio3: gpio@40b10000 { - compatible = "fsl,imx7ulp-gpio"; - reg = <0x40b10000 0x1000 0x400F00c0 0x40>; + gpio_ptf: gpio@40b10000 { + compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio"; + reg = <0x40b10000 0x1000 0x400f00c0 0x40>; gpio-controller; #gpio-cells = <2>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc1 0 96 32>; + clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>, + <&pcc3 IMX7ULP_CLK_PCTLF>; + clock-names = "gpio", "port"; + gpio-ranges = <&iomuxc1 0 96 20>; }; + };

- pmc0: pmc0@410a1000 { - compatible = "fsl,imx7ulp-pmc0"; - reg = <0x410a1000 0x1000>; - }; + m4aips1: bus@41080000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x41080000 0x80000>; + ranges;

sim: sim@410a3000 { compatible = "fsl,imx7ulp-sim", "syscon"; reg = <0x410a3000 0x1000>; };

- qspi1: qspi@410A5000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7ulp-qspi"; - reg = <0x410A5000 0x10000>, <0xC0000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7ULP_CLK_DUMMY>, - <&clks IMX7ULP_CLK_DUMMY>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - gpu: gpu@41800000 { - compatible = "fsl,imx6q-gpu"; - reg = <0x41800000 0x80000>, <0x41880000 0x80000>, - <0x60000000 0x40000000>, <0x0 0x4000000>; - reg-names = "iobase_3d", "iobase_2d", - "phys_baseaddr", "contiguous_mem"; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "irq_3d", "irq_2d"; - clocks = <&clks IMX7ULP_CLK_GPU3D>, - <&clks IMX7ULP_CLK_NIC1_DIV>, - <&clks IMX7ULP_CLK_GPU_DIV>, - <&clks IMX7ULP_CLK_GPU2D>, - <&clks IMX7ULP_CLK_NIC1_DIV>, - <&clks IMX7ULP_CLK_NIC1_DIV>; - clock-names = "gpu3d_clk", "gpu3d_shader_clk", - "gpu3d_axi_clk", "gpu2d_clk", - "gpu2d_shader_clk", "gpu2d_axi_clk"; + ocotp: efuse@410a6000 { + compatible = "fsl,imx7ulp-ocotp", "syscon"; + reg = <0x410a6000 0x4000>; + clocks = <&scg1 IMX7ULP_CLK_DUMMY>; }; }; - - imx_ion { - compatible = "fsl,mxc-ion"; - fsl,heap-id = <0>; - }; }; diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h index 0a955df4ad..b58370d146 100644 --- a/include/dt-bindings/clock/imx7ulp-clock.h +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -1,21 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright 2017~2018 NXP * */

#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H #define __DT_BINDINGS_CLOCK_IMX7ULP_H

+/* SCG1 */ + #define IMX7ULP_CLK_DUMMY 0 -#define IMX7ULP_CLK_CKIL 1 -#define IMX7ULP_CLK_OSC 2 +#define IMX7ULP_CLK_ROSC 1 +#define IMX7ULP_CLK_SOSC 2 #define IMX7ULP_CLK_FIRC 3 - -/* SCG1 */ #define IMX7ULP_CLK_SPLL_PRE_SEL 4 #define IMX7ULP_CLK_SPLL_PRE_DIV 5 #define IMX7ULP_CLK_SPLL 6 @@ -51,111 +49,71 @@ #define IMX7ULP_CLK_NIC1_DIV 36 #define IMX7ULP_CLK_NIC1_BUS_DIV 37 #define IMX7ULP_CLK_NIC1_EXT_DIV 38 +/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */ +#define IMX7ULP_CLK_MIPI_PLL 39 +#define IMX7ULP_CLK_SIRC 40 +#define IMX7ULP_CLK_SOSC_BUS_CLK 41 +#define IMX7ULP_CLK_FIRC_BUS_CLK 42 +#define IMX7ULP_CLK_SPLL_BUS_CLK 43 +#define IMX7ULP_CLK_HSRUN_SYS_SEL 44 +#define IMX7ULP_CLK_HSRUN_CORE_DIV 45

-/* PCG2 */ -#define IMX7ULP_CLK_DMA1 39 -#define IMX7ULP_CLK_RGPIO2P1 40 -#define IMX7ULP_CLK_FLEXBUS 41 -#define IMX7ULP_CLK_SEMA42_1 42 -#define IMX7ULP_CLK_DMA_MUX1 43 -#define IMX7ULP_CLK_SNVS 44 -#define IMX7ULP_CLK_CAAM 45 -#define IMX7ULP_CLK_LPTPM4 46 -#define IMX7ULP_CLK_LPTPM5 47 -#define IMX7ULP_CLK_LPIT1 48 -#define IMX7ULP_CLK_LPSPI2 49 -#define IMX7ULP_CLK_LPSPI3 50 -#define IMX7ULP_CLK_LPI2C4 51 -#define IMX7ULP_CLK_LPI2C5 52 -#define IMX7ULP_CLK_LPUART4 53 -#define IMX7ULP_CLK_LPUART5 54 -#define IMX7ULP_CLK_FLEXIO1 55 -#define IMX7ULP_CLK_USB0 56 -#define IMX7ULP_CLK_USB1 57 -#define IMX7ULP_CLK_USB_PHY 58 -#define IMX7ULP_CLK_USB_PL301 59 -#define IMX7ULP_CLK_USDHC0 60 -#define IMX7ULP_CLK_USDHC1 61 -#define IMX7ULP_CLK_WDG1 62 -#define IMX7ULP_CLK_WDG2 63 - -/* PCG3 */ -#define IMX7ULP_CLK_LPTPM6 64 -#define IMX7ULP_CLK_LPTPM7 65 -#define IMX7ULP_CLK_LPI2C6 66 -#define IMX7ULP_CLK_LPI2C7 67 -#define IMX7ULP_CLK_LPUART6 68 -#define IMX7ULP_CLK_LPUART7 69 -#define IMX7ULP_CLK_VIU 70 -#define IMX7ULP_CLK_DSI 71 -#define IMX7ULP_CLK_LCDIF 72 -#define IMX7ULP_CLK_MMDC 73 -#define IMX7ULP_CLK_PCTLC 74 -#define IMX7ULP_CLK_PCTLD 75 -#define IMX7ULP_CLK_PCTLE 76 -#define IMX7ULP_CLK_PCTLF 77 -#define IMX7ULP_CLK_GPU3D 78 -#define IMX7ULP_CLK_GPU2D 79 - -#define IMX7ULP_CLK_MIPI_PLL 80 -#define IMX7ULP_CLK_SIRC 81 +#define IMX7ULP_CLK_CORE 46 +#define IMX7ULP_CLK_HSRUN_CORE 47

-#define IMX7ULP_CLK_SCG1_CLKOUT 82 +#define IMX7ULP_CLK_SCG1_END 48

-#define IMX7ULP_CLK_END 83 +/* PCC2 */ +#define IMX7ULP_CLK_DMA1 0 +#define IMX7ULP_CLK_RGPIO2P1 1 +#define IMX7ULP_CLK_FLEXBUS 2 +#define IMX7ULP_CLK_SEMA42_1 3 +#define IMX7ULP_CLK_DMA_MUX1 4 +#define IMX7ULP_CLK_CAAM 6 +#define IMX7ULP_CLK_LPTPM4 7 +#define IMX7ULP_CLK_LPTPM5 8 +#define IMX7ULP_CLK_LPIT1 9 +#define IMX7ULP_CLK_LPSPI2 10 +#define IMX7ULP_CLK_LPSPI3 11 +#define IMX7ULP_CLK_LPI2C4 12 +#define IMX7ULP_CLK_LPI2C5 13 +#define IMX7ULP_CLK_LPUART4 14 +#define IMX7ULP_CLK_LPUART5 15 +#define IMX7ULP_CLK_FLEXIO1 16 +#define IMX7ULP_CLK_USB0 17 +#define IMX7ULP_CLK_USB1 18 +#define IMX7ULP_CLK_USB_PHY 19 +#define IMX7ULP_CLK_USB_PL301 20 +#define IMX7ULP_CLK_USDHC0 21 +#define IMX7ULP_CLK_USDHC1 22 +#define IMX7ULP_CLK_WDG1 23 +#define IMX7ULP_CLK_WDG2 24

-/*cm4 clocks*/ -#define IMX7ULP_CM4_CLK_DUMMY 0 -#define IMX7ULP_CM4_CLK_CKIL 1 -#define IMX7ULP_CM4_CLK_OSC 2 -#define IMX7ULP_CM4_CLK_FIRC 3 -#define IMX7ULP_CM4_CLK_SIRC 4 +#define IMX7ULP_CLK_PCC2_END 25

-/* SCG0 */ -#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL 5 -#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV 6 -#define IMX7ULP_CM4_CLK_SPLL 7 -#define IMX7ULP_CM4_CLK_SPLL_VCO 8 -#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1 9 -#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2 10 -#define IMX7ULP_CM4_CLK_SPLL_PFD0 11 -#define IMX7ULP_CM4_CLK_SPLL_PFD1 12 -#define IMX7ULP_CM4_CLK_SPLL_PFD2 13 -#define IMX7ULP_CM4_CLK_SPLL_PFD3 14 -#define IMX7ULP_CM4_CLK_SPLL_PFD_SEL 15 -#define IMX7ULP_CM4_CLK_SPLL_PFD 16 -#define IMX7ULP_CM4_CLK_SPLL_SEL 17 -#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL 18 -#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV 19 -#define IMX7ULP_CM4_CLK_APLL 20 -#define IMX7ULP_CM4_CLK_APLL_VCO 21 -#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1 22 -#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2 23 -#define IMX7ULP_CM4_CLK_APLL_PFD0 24 -#define IMX7ULP_CM4_CLK_APLL_PFD1 25 -#define IMX7ULP_CM4_CLK_APLL_PFD2 26 -#define IMX7ULP_CM4_CLK_APLL_PFD3 27 -#define IMX7ULP_CM4_CLK_APLL_PFD_SEL 28 -#define IMX7ULP_CM4_CLK_APLL_PFD 29 -#define IMX7ULP_CM4_CLK_APLL_SEL 30 -#define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV 31 -#define IMX7ULP_CM4_CLK_SYS_SEL 32 -#define IMX7ULP_CM4_CLK_CORE_DIV 33 -#define IMX7ULP_CM4_CLK_BUS_DIV 34 -#define IMX7ULP_CM4_CLK_PLAT_DIV 35 -#define IMX7ULP_CM4_CLK_SLOW_DIV 36 +/* PCC3 */ +#define IMX7ULP_CLK_LPTPM6 0 +#define IMX7ULP_CLK_LPTPM7 1 +#define IMX7ULP_CLK_LPI2C6 2 +#define IMX7ULP_CLK_LPI2C7 3 +#define IMX7ULP_CLK_LPUART6 4 +#define IMX7ULP_CLK_LPUART7 5 +#define IMX7ULP_CLK_VIU 6 +#define IMX7ULP_CLK_DSI 7 +#define IMX7ULP_CLK_LCDIF 8 +#define IMX7ULP_CLK_MMDC 9 +#define IMX7ULP_CLK_PCTLC 10 +#define IMX7ULP_CLK_PCTLD 11 +#define IMX7ULP_CLK_PCTLE 12 +#define IMX7ULP_CLK_PCTLF 13 +#define IMX7ULP_CLK_GPU3D 14 +#define IMX7ULP_CLK_GPU2D 15

-#define IMX7ULP_CM4_CLK_SAI0_SEL 37 -#define IMX7ULP_CM4_CLK_SAI0_DIV 38 -#define IMX7ULP_CM4_CLK_SAI0_ROOT 39 -#define IMX7ULP_CM4_CLK_SAI0_IPG 40 -#define IMX7ULP_CM4_CLK_SAI1_SEL 41 -#define IMX7ULP_CM4_CLK_SAI1_DIV 42 -#define IMX7ULP_CM4_CLK_SAI1_ROOT 43 -#define IMX7ULP_CM4_CLK_SAI1_IPG 44 +#define IMX7ULP_CLK_PCC3_END 16

-#define IMX7ULP_CLK_SCG0_CLKOUT 45 +/* SMC1 */ +#define IMX7ULP_CLK_ARM 0

-#define IMX7ULP_CM4_CLK_END 46 +#define IMX7ULP_CLK_SMC1_END 1

#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */