From: Chin Liang See chin.liang.see@intel.com
Add build support for Stratix SoC
Signed-off-by: Chin Liang See chin.liang.see@intel.com --- arch/arm/Kconfig | 8 +- arch/arm/mach-socfpga/Kconfig | 13 ++ configs/socfpga_stratix10_defconfig | 39 ++++++ include/configs/socfpga_stratix10_socdk.h | 216 ++++++++++++++++++++++++++++++ 4 files changed, 273 insertions(+), 3 deletions(-) create mode 100644 configs/socfpga_stratix10_defconfig create mode 100644 include/configs/socfpga_stratix10_socdk.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index bb64b9c..13dd144 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -655,21 +655,23 @@ config ARCH_SNAPDRAGON
config ARCH_SOCFPGA bool "Altera SOCFPGA family" - select CPU_V7 + select CPU_V7 if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select ARM64 if TARGET_SOCFPGA_STRATIX10 select SUPPORT_SPL select OF_CONTROL select SPL_OF_CONTROL select DM select DM_SPI_FLASH select DM_SPI - select ENABLE_ARM_SOC_BOOT0_HOOK + select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select ARCH_EARLY_INIT_R select ARCH_MISC_INIT select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION - select SYS_THUMB_BUILD + select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 imply CMD_MTDPARTS imply CRC32_VERIFY imply FAT_WRITE + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs" diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 45e5379..03ab956 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -49,6 +49,12 @@ config TARGET_SOCFPGA_GEN5 bool select ALTERA_SDRAM
+config TARGET_SOCFPGA_STRATIX10 + bool + select ARMV8_MULTIENTRY + select ARMV8_SPIN_TABLE + select ARMV8_SET_SMPEN + choice prompt "Altera SOCFPGA board select" optional @@ -86,6 +92,10 @@ config TARGET_SOCFPGA_SR1500 bool "SR1500 (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_STRATIX10_SOCDK + bool "Intel SOCFPGA SoCDK (Stratix 10)" + select TARGET_SOCFPGA_STRATIX10 + config TARGET_SOCFPGA_TERASIC_DE0_NANO bool "Terasic DE0-Nano-Atlas (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -116,12 +126,14 @@ config SYS_BOARD default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 + default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK + default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA @@ -145,6 +157,7 @@ config SYS_CONFIG_NAME default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 + default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig new file mode 100644 index 0000000..e5a7a69 --- /dev/null +++ b/configs/socfpga_stratix10_defconfig @@ -0,0 +1,39 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_FAT_SUPPORT=y +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_stratix10" +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk" +CONFIG_BOOTDELAY=5 +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_CMD_CACHE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_FS_GENERIC=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MII=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PING=y +CONFIG_CMD_SF=y +CONFIG_SPL=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DM_MMC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DFU_MMC=y +CONFIG_MMC_DW=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_CADENCE_QSPI=y +CONFIG_DM_ETH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_SYS_NS16550=y +CONFIG_USE_TINY_PRINTF=y diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h new file mode 100644 index 0000000..0d955f8 --- /dev/null +++ b/include/configs/socfpga_stratix10_socdk.h @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __CONFIG_SOCFGPA_STRATIX10_H__ +#define __CONFIG_SOCFGPA_STRATIX10_H__ + +#include <asm/arch/base_addr_s10.h> + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_TEXT_BASE 0x1000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_LOADADDR 0x80000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_REMAKE_ELF +#define CPU_RELEASE_ADDR 0x80 +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* + * U-Boot console configurations + */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ + +/* Extend size of kernel image for uncompression */ +#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) + +/* + * U-Boot run time memory configurations + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ + + CONFIG_SYS_INIT_RAM_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) +#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) + +/* + * U-Boot display configurations + */ +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* + * U-Boot environment configurations + */ +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + +/* + * QSPI support + */ + #ifdef CONFIG_CADENCE_QSPI +/* Enable it if you want to use dual-stacked mode */ +#undef CONFIG_SF_DUAL_FLASH +/*#define CONFIG_QSPI_RBF_ADDR 0x720000*/ + +/* Flash device info */ +#define CONFIG_SF_DEFAULT_SPEED (50000000) +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_3 | SPI_RX_QUAD) +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 + +/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/ +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH +#undef CONFIG_ENV_OFFSET +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET 0x710000 +#define CONFIG_ENV_SIZE (4 * 1024) +#define CONFIG_ENV_SECT_SIZE (4 * 1024) +#endif /* CONFIG_ENV_IS_IN_SPI_FLASH */ + +/*#define CONFIG_BOOT_FLASH_TYPE "qspi"*/ +#define CONFIG_CQSPI_DECODER 0 + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nor0=ff705000.spi.0" +#endif /* CONFIG_SPL_BUILD */ + +/* 533MHz, TODO: Get from SDM */ +#define CONFIG_CQSPI_REF_CLK 400000000 + +#endif /* CONFIG_CADENCE_QSPI */ + +/* + * Boot arguments passed to the boot command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will overide also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "earlycon" +#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=Image\0" \ + "fdt_addr=8000000\0" \ + "fdtimage=socfpga_stratix10_socdk.dtb\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "booti ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootfile};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" + +/* + * Generic Interrupt Controller Definitions + */ +#define CONFIG_GICV2 + +/* + * External memory configurations + */ +#define PHYS_SDRAM_1 0x0 +#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_MEMTEST_START 0 +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000 + +/* + * SDRAM controller + */ +#define CONFIG_ALTERA_SDRAM + +/* + * Serial / UART configurations + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS +#define CONFIG_SYS_NS16550_CLK 100000000 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +/* always write in 32 bit manner */ +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_REG_SIZE -4 + +/* + * Timer & watchdog configurations + */ +#define COUNTER_FREQUENCY 400000000 + + +/* + * SDMMC configurations + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 +#endif +/* + * Flash configurations + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_MII +#define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) +#define CONFIG_PHY_GIGE +#endif /* CONFIG_CMD_NET */ + + +/* + * SPL memory layout + * + * On chip RAM + * 0xFFE0_0000 ...... Start of OCRAM + * SPL code, rwdata + * 0xFFEx_xxxx ...... Top of stack (grows down) + * 0xFFEy_yyyy ...... Global Data + * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN) + * 0xFFE3_FFFF ...... End of OCRAM + * + * SDRAM + * 0x0000_0000 ...... Start of SDRAM_1 + * unused / empty space for image loading + * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE) + * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE) + * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) + * + */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \ + - CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \ + - CONFIG_SYS_SPL_MALLOC_SIZE) +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x400000 + +/* SPL SDMMC boot support */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" + +#endif /* __CONFIG_H */